AM79C971VCW datasheet(145/265 Pages) AMD

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Am79C971

145

P R E L I M INARY

15-0

TXDAPL

Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If the

previous transmit frame did not

use buffer chaining, then TXDA-

PL contains the lower 16 bits of

the previous frame’s transmit de-

scriptor address.

When both the STOP or SPND

bits are cleared, this register is

updated by Am79C971 controller

immediately before a transmit de-

scriptor write.

Read accessible always. Write

accessible through the PXDAL

bits (CSR60) when the STOP or

SPND bit is set. TXDAPL is set to

0 by H_RESET and are unaffect-

ed by S_RESET or STOP.

CSR84: DMA Address Register Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAL

This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAL register is undefined

until the first Am79C971 control-

ler DMA operation.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR85: DMA Address Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAU

This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAU register is undefined

until the first Am79C971 control-

ler DMA operation.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR86: Buffer Byte Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved. Read and written with

ones.

11-0

DMABC

DMA Byte Count Register. Con-

tains the two's complement of the

current size of the remaining

transmit

or receive

buffer in

bytes. This register is increment-

ed by the Bus Interface Unit. The

DMABC register is undefined un-

til written.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR88: Chip ID Register Lower

Bit

Name

Description

31-28 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

27-12 PARTID

Part number. The 16-bit code for

the Am79C971 controller is 0010

0110 0010 0011b (2623h).

This register is exactly the same

as the Device ID register in the

JTAG description. It is, however,

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