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AM79C971VCW 数据表(PDF) 147 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 147 Page - Advanced Micro Devices |
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147 / 265 page  Am79C971 147 P R E L I M INARY Read/Write accessible only when either the STOP or the SPND bit is set. This register is set to 0600h by H_RESET or S_RESET and is unaffected by STOP. CSR112: Missed Frame Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 MFC Missed Frame Count. Indicates the number of missed frames. MFC will roll over to a count of 0 from the value 65535. The MFCO bit of CSR4 (bit 8) will be set each time that this occurs. Read accessible always. MFC is read only, write operations are ig- nored. MFC is cleared by H_RESET or S_RESET or by setting the STOP bit. CSR114: Receive Collision Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCC Receive Collision Count. Indi- cates the total number of colli- sions encountered by the receiver since the last reset of the counter. RCC will roll over to a count of 0 from the value 65535. The RCVCCO bit of CSR4 (bit 5) will be set each time that this occurs. Read accessible always. RCC is read only, write operations are ig- nored. RCC is cleared by H_RESET or S_RESET, or by setting the STOP bit. CSR122: Advanced Feature Control Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-1 RES Reserved locations. Written as zeros and read as undefined. 0 RCVALGN Receive Packet Align. When set, this bit forces the data field of ISO 8802-3 (IEEE/ANSI 802.3) pack- ets to align to 0. MOD 4 address boundaries (i.e., DWord aligned addresses). It is important to note that this feature will only function correctly if all receive buffer boundaries are DWord aligned and all receive buffers have 0 MOD 4 lengths. In order to ac- complish the data alignment, the Am79C971 controller simply in- serts two bytes of random data at the beginning of the receive pack- et (i.e., before the ISO 8802-3 (IEEE/ANSI 802.3) destination address field). The MCNT field reported to the receive descriptor will not include the extra two bytes. Read/Write accessible always. RCVALGN is cleared by H_RESET or S_RESET and is not affected by STOP. CSR124: Test Register 1 This register is used to place the Am79C971 controller into various test modes. The Runt Packet Accept is the only user accessible test mode. All other test modes are for AMD internal use only. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-4 RES Reserved locations. Written as zeros and read as undefined. 3 RPA Runt Packet Accept. This bit forces the Am79C971 controller to accept runt packets (packets shorter than 64 bytes). Read accessible always; write accessible only when STOP is set to 1. RPA is cleared by H_RESET or S_RESET and is not affected by STOP. 2-0 RES Reserved locations. Written as zeros and read as undefined. CSR125: MAC Enhanced Configuration Control Bit Name Description |
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