AM79C971VCW datasheet(150/265 Pages) AMD

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Am79C971

P R E L I M INARY

BCR1: Master Mode Write Active

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

MSWRA

Reserved

locations.

After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this register has no effect on any

Am79C971 controller function. It

is only included for software com-

patibility with other PCnet family

devices.

Read always. MSWRA is read

only. Write operations have no ef-

fect.

BCR2: Miscellaneous Configuration

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

RES

Reserved location. Written and

read as zeros.

TMAULOOP

When set, this bit allows external

loopback packets to pass onto

the network through the T-MAU

interface, if the T-MAU interface

has been selected. If the T-MAU

interface has not been selected,

then this bit has no effect.

Read/Write accessible always.

TMAULOOP is reset to 0 by

H_RESET and is unaffected by

S_RESET or STOP.

RES

Reserved location. Written and

read as zero.

LEDPE

LED

Program

Enable.

When

LEDPE is set to 1, programming

the

LED0

(BCR4),

LED1

(BCR5),

LED2

(BCR6),

and

LED3 (BCR7) registers is en-

abled. When LEDPE is cleared to

0, programming of LED0 (BCR4),

LED1 (BCR5), LED2 (BCR6),

and LED3 (BCR7) registers is

disabled. Writes to those regis-

ters will be ignored.

Read/Write accessible always.

LEDPE

cleared

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

11-9

RES

Reserved locations. Written and

read as zeros.

APROMWE Address PROM Write Enable.

The Am79C971 controller con-

tains a shadow RAM on board for

storage of the first 16 bytes load-

ed from the serial EEPROM.

Accesses to Address PROM I/O

Resources will be directed toward

this RAM. When APROMWE is

set to 1, then write access to the

shadow RAM will be enabled.

Read/Write accessible always.

APROMWE is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

INTLEVEL

Interrupt Level. This bit allows the

interrupt output signals to be pro-

grammed

for

level

edge-

sensitive applications.

When INTLEVEL is cleared to 0,

the INTA pin is configured for

level-sensitive

applications.

this mode, an interrupt request is

signaled by a low level driven on

the INTA pin by the Am79C971

controller. When the interrupt is

cleared, the INTA pin is tri-stated

by the Am79C971 controller and

allowed to be pulled to a high lev-

el by an external pullup device.

This mode is intended for sys-

tems which allow the interrupt

signal to be shared by multiple

devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive

applications.

this

mode, an interrupt request is sig-

naled by a high level driven on

the INTA pin by the Am79C971

controller. When the interrupt is

cleared, the INTA pin is driven to

a low level by the Am79C971

controller. This mode is intended

for systems that do not allow

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