AM79C971VCW datasheet(138/265 Pages) AMD

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138

Am79C971

The default value of this register

is 0000b. This corresponds to a

polling interval of 65,536 clock

periods

(1.966

when

CLK = 33 MHz). The TXPOL-

LINT value of 0000b is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR47 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the stan-

dard

initialization

procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is imperative that the user

also writes all zeros to CSR47 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR48: Receive Poll Time Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLL

Receive Poll Time Counter. This

counter is incremented by the

Am79C971 controller microcode

and is used to trigger the receive

descriptor ring polling operation

of the Am79C971 controller.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR49: Receive Polling Interval

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C971 controller will wait be-

tween successive polling opera-

tions. The RXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of RXPOLLINT

approximately

represents

one

clock

time

period.

RXPOL-

LINT[3:0] are ignored. (RXPOL-

LINT[16] is implied to be a 1, so

RXPOLLINT[15]

significant

and does not represent the sign

of the two’s complement RXPOL-

LINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods

(1.966

when

CLK = 33 MHz). The RXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR49 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for RXPOLLINT other than

the default, then the correct pro-

cedure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR49 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

AM79C971VCW 数据表(PDF) 138 Page - Advanced Micro Devices

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