AM79C971VCW datasheet(132/265 Pages) AMD

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132

Am79C971

Table 26.

Network Port Configuration.

DRTY

Disable Retry. When DRTY is set

to 1, the Am79C971 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwritten, because auto-

matic retransmission will not be

necessary. When DRTY is set to

0, the Am79C971 controller will

attempt 16 transmissions before

signaling a retry error.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The Am79C971 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back

transmission

attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Collision

logic will be disabled. FCOLL is

defined

after

the

initialization

block is read.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with

the

transmitted

frame.

DXMTFCS is overridden when

ADD_FCS is set in TMD1.

When APAD_XMT (CSR4, bit

11) is set to 1, the setting of

DXMTFCS has no effect on

frames shorter than 64 bytes.

DXMTFCS

set

and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

The value of ADD_FCS is valid

only when STP is set in TMD1. If

ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

LOOP

Loopback

Enable

allows

the

Am79C971 controller to operate

in full-duplex mode for test pur-

poses. The setting of the full-

duplex control bits in BCR9 have

no effect when the device oper-

ates in loopback mode. When

LOOP = 1, loopback is enabled.

In combination with INTL and

MENDECL,

various

loopback

modes are defined as follows in

Table 27. Refer to Loop Back Op-

eration section for more details.

PORTSEL [1:0]

ASEL

(BCR2[1])

Link Status

(10BASE-T)

MII Status

(BCR32[14])

Network

Port

Fail

AUI

Pass

10BASE-T

Don’t Care

MII

Don’t Care

AUI

Don’t Care

10BASE-T

Don’t Care

GPSI

Don’t Care

MII

Table 27.

Loopback Configuration for AUI

LOOP

INTL

MENDECL

Loopback Mode

Non-loopback

External Loopback

Internal Loopback Include

MENDEC

Internal Loopback

Exclude MENDEC

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