AM79C971VCW datasheet(123/265 Pages) AMD

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Am79C971

123

JAB

Jabber

Error

set

the

Am79C971 controller when the

T-MAU

exceeds

the

allowed

transmission limit. Jabber can

only be asserted in 10BASE-T

mode.

When JAB is set, INTA is assert-

ed if IENA is 1 and the mask bit

JABM is 0.

Read/Write accessible always.

JAB is cleared by the host by writ-

ing a 1. Writing a 0 has no effect.

JAB is cleared by H_RESET,

S_RESET or by setting the STOP

bit.

JABM

Jabber Error Mask. If JABM is

set, the JAB bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

JABM is set to 1 by H_RESET or

S_RESET and is not affected by

the STOP bit.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

TOKINTD

Transmit OK Interrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission

was

successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5, bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independent

of the success of the transmis-

sion.

Read/Write accessible always.

TOKINTD

cleared

H_RESET or S_RESET and is

unaffected by STOP.

LTINTEN

Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will cause the Am79C971 control-

ler to read bit 28 of TMD1 as

LTINT. The setting LTINT will de-

termine if TINT will be set at the

end of the transmission.

Read/Write accessible always.

LTINTEN

cleared

H_RESET or S_RESET and is

unaffected by STOP.

13-12

RES

Reserved locations. Written as

zeros and read as undefined.

SINT

System Interrupt is set by the

Am79C971 controller when it de-

tects a system error during a bus

master transfer on the PCI bus.

System errors are data parity er-

ror, master abort, or a target

abort. The setting of SINT due to

data parity error is not dependent

on the setting of PERREN (PCI

Command register, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system error.

Read/Write accessible always.

SINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. The state of SINT is not af-

fected by clearing any of the PCI

Status register bits that get set

when

data

parity

error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

SINTE

System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible always.

SINTE is set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

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