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AM79C971VCW 数据表(PDF) 157 Page - Advanced Micro Devices

部件名 AM79C971VCW
功能描述  PCnet??FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
PDF  265 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 157 Page - Advanced Micro Devices

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Am79C971
157
P R E L I M INARY
5
RCVME
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network that has
passed the address match func-
tion for this node. All address
matching modes are included:
physical, logical filtering, broad-
cast, and promiscuous.
Read/Write accessible always.
RCVME is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
Read/Write accessible always.
XMTE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
3
RXPOLE
Receive Polarity Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when normal polarity of
the RXD
± pair has not been re-
versed.
Receive polarity indication is val-
id only if the T-MAU is in link pass
state.
Read/Write accessible always.
RXPOLE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
2
RCVE
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network.
Read/Write accessible always.
RCVE is set to 1 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
1
JABE
Jabber Status Enable. When this
bit is set, a value of 1 is passed to
the LEDOUT bit in this register
when the Am79C971 controller is
jabbering on the network.
Read/Write accessible always.
JABE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network. The activ-
ity on the collision inputs to the
AUI port within the first 4
µs after
every transmission for the pur-
pose of SQE testing will not
cause the LEDOUT bit to be set.
Read/Write accessible always.
COLE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
BCR6: LED2 Status
BCR6 controls the function(s) that the LED2 pin dis-
plays. Multiple functions can be simultaneously en-
abled on this LED pin. The LED display will indicate the
logical OR of the enabled functions. BCR6 defaults to
Receive Polarity Status (RXPOL) with pulse stretcher
enabled (PSE = 1) and is fully programmable.
Note: When LEDPE (BCR2, bit 12) is set to 1, pro-
gramming of the LED2 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED2 register is disabled. Writes to those registers will
be ignored.
Note: Bits 15-0 in this register are programmable
through the EEPROM PREAD operation.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
LEDOUT
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the en-
abled signals is true.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
Read accessible always. This bit
is read only; writes have no ef-
fect. LEDOUT is unaffected by
H_RESET, S_RESET, or STOP.



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