AM79C971VCW datasheet(158/265 Pages) AMD

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158

Am79C971

P R E L I M INARY

LEDPOL

LED Polarity. When this bit has

the value 0, then the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole output and the output value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

LEDDIS

LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by the LEDOUT

and LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

100E

100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C971 controller is

operating at 100 Mbps mode. The

indication is valid with both the in-

ternal and external PHYs.

Read/Write accessible always.

100E is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

MIISE

Media Independent Interface Se-

lected Enable. Indicates when the

MII interface is selected. This will

be set when either the Manage-

ment Port State Machine is se-

lecting the MII or when ASEL

(BCR2, bit1) is disabled and

PORTSEL (CSR15, bits 8-7) se-

lects the MII. This could control

relays to switch in and out appro-

priate filters or could control an

external PHY when sharing an

RJ45 connector.

Read/Write accessible always.

MIISE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

DXCVRCTL

DXCVR Control. When the AUI

interface is the active network

port, DXCVRCTL controls the as-

sertion of the LED2 output. The

polarity of the asserted state is

controlled by the LEDPOL bit

(BCR4, bit 14). The LED2 pin can

be used to control a DC-to-DC

converter

applications

that

want to connect a 10BASE2

MAU, as well as a standard DB15

AUI connector to the Am79C971

AUI port. When DXCVRCTL is

set to 1, the LED2 output will be

asserted. This could be used to

enable a DC-to-DC converter for

10BASE2 MAUs (assuming the

enable input of the DC-to-DC

converter is active high and LED-

POL is cleared to 0). When DX-

CVRCTL is cleared to 0, the

LED2 output will be deasserted.

This would power down the DC-

to-DC

converter.

When

the

10BASE-T interface is the active

network port, the DXCVR output

is always deasserted.

Read/Write accessible always.

DXCVRCTL

cleared

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

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