AM79C971VCW datasheet(164/265 Pages) AMD

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164

Am79C971

P R E L I M INARY

4-0

RES

Reserved locations. Written as

zeros, read as undefined.

BCR17: I/O Base Address Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

IOBASEU

Reserved

locations.

After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this register will have no effect

any

Am79C971

controller

function. It is only included for

software compatibility with other

PCnet family devices.

Read/Write accessible always.

IOBASEU is not affected by

S_RESET or STOP.

BCR18: Burst and Bus Control Register

Note: Note that bits 15-0 in this register are program-

mable through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 ROMTMG

Expansion ROM Timing. The val-

ue of ROMTMG is used to tune

the

timing

for

all

EBDATA

(BCR30) accesses to SRAM/

Flash/EPROM as well as all Ex-

pansion ROM accesses to Flash/

EPROM.

ROMTMG, during read opera-

tions, defines the time from when

the Am79C971 controller drives

the lower 8 or 16 bits of the Ex-

pansion Bus Address bus to

when the Am79C971 controller

latches in the data on the 8 or 16

bits of the Expansion Bus Data

inputs. ROMTMG, during write

operations, defines the time from

when the Am79C971 controller

drives the lower 8 or 16 bits of the

Expansion Bus Data to when the

EBWE and EROMCS deassert.

The differences in the sizes of the

Expansion

Bus

Address

and

Data busses is due to the differ-

ence in the access for SRAM ver-

sus Flash/EPROM.

The register value specifies the

time in number of clock cycles +1

according to Table 33.

Note: Programming ROMTNG

with a value of 0 is not permitted.

The access time for the Expan-

sion

ROM

the

EDBATA

(BCR30) device (tACC) during

read operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA_EBA[7:0]

outputs (tv_A_D) and by subtract-

ing the input to clock setup time

for the EBD[7:0] inputs (ts_D)

from the time defined by ROMT-

MG:

tACC = ROMTMG * CLK period

*CLK_FAC - (tv_A_D) - (ts_D)

The access time for the Expan-

sion ROM or for the EDBATA

(BCR30) device (tACC) during

write operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA EBA[7:0]

outputs (tv_A_D) and by adding

the input to clock setup time for

SRAM/Flash/EPRO inputs (ts_D)

from the time defined by ROMT-

MG:

tACC = ROMTMG * CLK period *

CLK_FAC - (tv_A_D) - (ts_D)

Table 32.

Network Port Configuration

AUIFD

(bit

FDEN

(bit

Effect on the AUI

Port

Effect on the

10BASE-T Port

Effect on the GPSI

Port

Effect On the MII Port (ASEL =

0, PORTSEL = MII)

Half-Duplex

Full-Duplex

Table 33.

ROMTNG Programming Values

ROMTMG (bits 15-12)

No. of Expansion Bus Cycles

1h<=n <=Fh

n+1

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