AM79C971VCW datasheet(167/265 Pages) AMD

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Am79C971

167

P R E L I M INARY

BCR19: EEPROM Control and Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PVALID

EEPROM Valid status bit. Read

accessible only. PVALID is read

only; write operations have no ef-

fect. A value of 1 in this bit indi-

cates that a PREAD operation

has occurred, and that (1) there is

an EEPROM connected to the

Am79C971 controller interface

pins and (2) the contents read

from the EEPROM have passed

the checksum verification opera-

tion.

A value of 0 in this bit indicates a

failure in reading the EEPROM.

The checksum for the entire 64

bytes of EEPROM is incorrect or

no EEPROM is connected to the

interface pins.

PVALID

set

during

H_RESET and is unaffected by

S_RESET or the STOP bit. How-

ever, following the H_RESET op-

eration, an automatic read of the

EEPROM will be performed. Just

as is true for the normal PREAD

command, at the end of this auto-

matic read operation, the PVALID

bit may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter

H_RESET,

requested

through PREAD), then all EE-

PROM-programmable BCR loca-

tions

will

reset

their

H_RESET values. The content of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to the automatic read of the

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

PREAD

EEPROM Read command bit.

When this bit is set to a 1 by the

host, the PVALID bit (BCR19, bit

15) will immediately be reset to a

0, and then the Am79C971 con-

troller will perform a read opera-

tion

bytes

from

the

EEPROM through the interface.

The

EEPROM

data

that

fetched during the read will be

stored in the appropriate internal

registers

board

the

Am79C971 controller. Upon com-

pletion of the EEPROM read op-

eration, the Am79C971 controller

will assert the PVALID bit. EE-

PROM contents will be indirectly

accessible to the host through

read accesses to the Address

PROM (offsets 0h through Oh)

and through read accesses to

other EEPROM programmable

registers. Note that read access-

es from these locations will not

actually access the EEPROM it-

self, but instead will access the

Am79C971 controllers internal

copy of the EEPROM contents.

Write accesses to these locations

may change the Am79C971 con-

troller register contents, but the

EEPROM locations will not be af-

fected. EEPROM locations may

accessed

directly

through

BCR19.

At the end of the read operation,

the PREAD bit will automatically

be reset to a 0 by the Am79C971

controller and PVALID will bet

set, provided that an EEPROM

existed on the interface pins and

that the checksum for the entire

64 bytes of EEPROM was cor-

rect.

Note that when PREAD is set to a

1, then the Am79C971 controller

will no longer respond to any ac-

cesses directed toward it, until

the PREAD operation has com-

pleted

successfully.

The

Am79C971 controller will termi-

nate these accesses with the as-

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