AM79C970 datasheet(33/168 Pages) AMD

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Am79C970

Initialization Block DMA Transfers

During execution of the PCnet-PCI controller bus mas-

ter initialization procedure, the PCnet-PCI microcode

will repeatedly request DMA transfers from the BIU.

During each of these initialization block DMA transfers,

the BIU will perform two data transfer cycles (eight

bytes) and then it will relinquish the bus. The two trans-

fers within the mastership period will always be read cy-

cles to ascending contiguous addresses. When

SSIZE32 = 1 (BCR20, bit 8), there are 7 DWORDs to

transfer during the bus master initialization procedure,

so four bus mastership periods are needed in order to

complete the initialization sequence. Note that the last

DWORD transfer of the last bus mastership period of the

initialization sequence accesses an unneeded location.

Data from this transfer is discarded internally. When

SSIZE32 = 0 (BCR20, bit 8), then three bus mastership

periods are needed to complete the initialization

sequence.

18220C-15

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

12345678

IADD

0000

0110

PAR

DATA

0000

0110

PAR

DEVSEL is sampled by the PCnet-PCI controller.

IADD +4

Figure 13. Initialization Block Read

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