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AM79C970 数据表(PDF) 99 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 99 Page - Advanced Micro Devices |
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99 / 168 page  AMD P R E L I M I N A R Y 1-966 Am79C970 15–0 NNXDAU Contains the upper 16 bits of the next next transmit descriptor ad- dress pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR40: Current Receive Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZERO. 11–0 CRBC Current Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the current re- ceive descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR41: Current Receive Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 CRST Current Receive Status. This field is a copy of bits 31–24 of RMD1 of the current receive descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. 7–0 RES Reserved locations. Read and written as ZERO. CSR42: Current Transmit Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZERO. 11–0 CXBC Current Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the current trans- mit descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR43: Current Transmit Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 CXST Current Transmit Status. This field is a copy of bits 31–24 of TMD1 of the current transmit descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. 7–0 RES Reserved locations. Read and written as ZERO. CSR44: Next Receive Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZERO. 11–0 NRBC Next Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the next receive descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR45: Next Receive Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 NRST Next Receive Status. This field is a copy of bits 31–24 of RMD1 of the next receive descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. 7–0 RES Reserved locations. Read and written as ZERO. |
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