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AM79C970 数据表(PDF) 97 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 97 Page - Advanced Micro Devices |
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97 / 168 page  AMD P R E L I M I N A R Y 1-964 Am79C970 Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR24: Base Address of Receive Ring Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 BADRL Contains the lower 16 bits of the base address of the Receive Ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR25: Base Address of Receive Ring Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 BADRU Contains the upper 16 bits of the base address of the Receive Ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR26: Next Receive Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRDAL Contains the lower 16 bits of the next RDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR27: Next Receive Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRDAU Contains the upper 16 bits of the next RDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR28: Current Receive Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CRDAL Contains the lower 16 bits of the current RDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR29: Current Receive Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CRDAU Contains the upper 16 bits of the current RDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR30: Base Address of Transmit Ring Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 BADXL Contains the lower 16 bits of the base address of the Transmit Ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR31: Base Address of Transmit Ring Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 BADXU Contains the upper 16 bits of the base address of the Transmit Ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. |
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