AM79C970 datasheet(41/168 Pages) AMD

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AMD

P R E L I M I N A R Y

1-908

Am79C970

Figure 17 shows a partial linear burst that occurred while

approaching the transfer of the last bytes of data to a RX

buffer. The linear burst begins when 10 bytes of space

still remain in the RX buffer. (The number of spaces re-

maining for the figure as drawn could be anywhere from

9 to 12. The value of 10-byte spaces has been chosen

just for purposes of illustration.) After the first linear

burst transfer, 6 byte spaces remain. Knowing that the

second transfer will use another 4 bytes of space, the

PCnet-PCI controller is able to predict that the third

transfer will be the last. Therefore, it de-asserts

FRAME

on the second transfer to terminate the linear burst op-

eration. However, the PCnet-PCI controller retains own-

ership of the bus so that it may, immediately, make

non-burst transfer(s) to the last two spaces in the buffer.

18220C-19

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

12345678

n00h

DATA

n08h

0000

0111

PAR

DEVSEL is sampled by the PCnet-PCI controller.

DATA

1100

0111

PAR

Figure 17. Partial Linear Burst at the End of Buffer

If a burst cycle is preempted before the last data phase,

the PCnet-PCI controller will finish the current data

phase and release the bus.

REQ will stay asserted. The

PCnet-PCI controller will revert to non-burst cycle

accesses following the preemption event. In this case,

linear bursting will next occur when the memory address

being accessed next meets the linear burst starting ad-

dress requirements.

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