AM79C970 datasheet(73/168 Pages) AMD

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AMD

P R E L I M I N A R Y

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Am79C970

goes inactive (this does not apply if the 10BASE-T port

is selected). If the CI

± input is not asserted within the 40

network bit time period following the completion of

transmission, then the PCnet-PCI controller will set the

CERR bit in CSR0. CERR will be asserted in 10BASE-T

mode after transmit if T-MAU is in Link Fail state. CERR

will never cause

INTA to be activated. It will, however,

set the ERR bit CSR0.

Receive Operation

The receive operation and features of the PCnet-PCI

controller are controlled by programmable options.

Address Matching

The PCnet-PCI controller supports three types of ad-

dress matching: unicast, multicast, and broadcast. The

normal address matching procedure can be modified by

programming three bits in the MODE register (PROM,

DRCVBC, and DRCBC).

If the first bit received after the start of frame delimiter

(the least significant bit of the first byte of the destination

address field) is 0, the frame is unicast, which indicates

that the frame is meant to be received by a single node.

If the first bit received is 1, the frame is multicast, which

indicates that the frame is meant to be received by a

group of nodes. If the destination address field contains

all ones, the frame is broadcast, which is a special type

of multicast. Frames with the broadcast address in the

destination address field are meant to be received by all

nodes on the local area network.

When a unicast frame arrives at the PCnet-PCI control-

ler, the controller will accept the frame if the destination

address field of the incoming frame exactly matches the

6-byte station address stored in the PADR registers

(CSR12, CSR13, and CSR14). The byte ordering is

such that the first byte received from the network (after

the SFD) must match the least significant byte of CSR12

(PADR[7:0]), and the sixth byte received must match the

most significant byte of CSR14 (PADR[47:40]).

If DRCVPA (bit 13 in the MODE register) is set. the

PCnet-PCI controller will not accept unicast frames.

If the incoming frame is multicast the PCnet-PCI control-

ler performs a calculation on the contents of the destina-

tion address field to determine whether or not to accept

the frame. This calculation is explained in the section

that describes the Logical Address Filter (LADRF).

If all bits of the LADRF registers are 0 no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

PCnet-PCI controller hardware. Broadcast frames are

always accepted, except when DRCVBC (bit 14 in the

MODE register) is set.

None of the address filtering described above applies

when the PCnet-PCI controller is operating in the pro-

miscuous mode. In the promiscuous mode, all properly

formed packets are received, regardless of the contents

of their destination address fields. The promiscuous

mode overrides the Disable Receive Broadcast bit

(DRCVBC bit l4 in the MODE register) and the Disable

Receive Physical Address bit (DRCVPA, bit 13 MODE

The PCnet-PCI controller operates in promiscuous

mode when PROM (bit 15 in the MODE register) is set.

Receive Function Programming

Automatic pad field stripping is enabled by setting the

ASTRP_RCV bit in CSR4. This can provide flexibility in

the reception of messages using the 802.3 frame

format.

All receive frames can be accepted by setting the PROM

bit in CSR15. When PROM is set, the PCnet-PCI con-

troller will attempt to receive all messages, subject to

minimum frame enforcement. Promiscuous mode over

rides the effect of the Disable Receive Broadcast bit on

receiving broadcast frames.

The point at which the BMU will start to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established dur-

ing H_RESET is 10b which sets the threshold flag at

64 bytes empty.

Automatic Pad Stripping

During reception of an 802.3 frame the pad field can be

stripped automatically. ASTRP_RCV (CSR4, bit 0) = 1

enables the automatic pad stripping feature. The pad

field will be stripped before the frame is passed to the

FIFO, thus preserving FIFO space for additional frames.

The FCS field will also be stripped, since it is computed

at the transmitting station based on the data and pad

field characters, and will be invalid for a receive frame

that has had the pad characters stripped.

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the ISO 8802-3

(IEEE/ANSI 802.3) definition) contained in the frame.

The length indicates the actual number of LLC data

bytes contained in the message. Any received frame

which contains a length field less than 46 bytes will have

the pad field stripped (if ASTRP_RCV is set). Receive

frames which have a length field of 46 bytes or greater

will be passed to the host unmodified.

Since any valid Ethernet Type field value will always be

greater than a normal 802.3 Length field (

≥46), the

PCnet-PCI controller will not attempt to strip valid Ether-

net frames.

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