AM79C970 datasheet(67/168 Pages) AMD

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Am79C970

Table 6 describes all possible bus master accesses that

the PCnet-PCI controller will perform. The right most

column lists all operations that may execute the given

access:

Table 6. Bus Master Accesses

Access

Mode

BE[3:0]

Operation

4-byte read

Read

0000

descriptor read

or initialization block read

or transmit data buffer read

4-byte write

Write

0000

descriptor write

or receive data buffer write

3-byte write

Write

1000

receive data buffer write

3-byte write

Write

0001

receive data buffer write

2-byte write

Write

1100

receive data buffer write

2-byte write

Write

1001*

receive data buffer write

2-byte write

Write

0011

receive data buffer write

1-byte write

Write

1110

receive data buffer write

1-byte write

Write

1101*

receive data buffer write

1-byte write

Write

1011*

receive data buffer write

1-byte write

Write

0111

descriptor write

or receive data buffer write

* Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte

buffer sizes, and therefore will not be seen under normal circumstances.

Note that all PCnet-PCI controller master read opera-

tions will always activate all byte enables. Therefore, no

one-, two- or three-byte read operations are indicated in

the table.

In the instance where a transmit buffer pointer address

begins on a non-DWORD boundary, the pointer will be

truncated to the next DWORD boundary address that

lies below the given pointer address and the first read

access from the transmit buffer will be indicated on the

byte enable signals as a four-byte read from this ad-

dress. Any data from byte lanes that lie outside of the

boundary indicated by the buffer pointer will be dis-

carded inside of the PCnet-PCI controller. Similarly, if

the end of a transmit buffer occurs on a non-DWORD

boundary, then all byte lanes will be indicated as active

by the byte enable signals, and any data from byte lanes

that lie outside of the boundary indicated by the buffer

pointer will be discarded inside of the PCnet-PCI

controller.

Slave Access to I/O Resources

The PCnet-PCI device is always a 32-bit peripheral on

the system bus. However, the width of individual soft-

ware resources on board the PCnet-PCI controller may

be either 16-bits or 32-bits. The PCnet-PCI controller

I/O resource widths are determined by the setting of the

DWIO bit as indicated in the following table:

PCnet-PCI

Controller I/O

DWIO Setting Resource Width

Example Application

DWIO = 0

16-bit

Existing PCnet-ISA

driver that assumes

16-bit I/O mapping

and 16-bit resource

widths

DWIO = 1

32-bit

New drivers written

specifically for the

PCnet-PCI controller

Note that when I/O resource width is defined as 32 bits

(DWIO mode), the upper 16 bits of the I/O resource is

reserved and written as ZEROS and read as undefined,

except for the APROM locations and CSR88

. The

APROM locations and CSR88 are the only I/O re-

sources for which all 32 bits will have defined values.

However, this is true only when the PCnet-PCI controller

is in DWIO mode.

Configuring the PCnet-PCI controller for DWIO mode is

accomplished whenever there is any attempt to perform

a 32-bit write access to the RDP location (offset 10h).

See the DWIO section for more details.

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