AM79C970 datasheet(72/168 Pages) AMD

72 / 168 page

P R E L I M I N A R Y

AMD

1-939

Am79C970

The 544 bit count is derived from the following:

Minimum frame

size (excluding

preamble,

including FCS)

bytes

512

bits

Preamble/SFD size

bytes

bits

FCS size

bytes

bits

To be classed as a minimum size frame at the receiver,

the transmitted frame must contain:

Preamble + (Min Frame Size + FCS) bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble + (Min Frame Size – FCS) bits

64 + (512 – 32) bits

A minimum length transmit frame from the PCnet-PCI

controller will therefore be 576 bits, after the FCS is

appended.

The Ethernet specification assumes that minimum

length messages will be at least 64 bytes in length.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS bit in

CSR15. When DXMTFCS = 0 the transmitter will gener-

ate and append the FCS to the transmitted frame. If the

automatic padding feature is invoked (APAD_XMT is

set in CSR4), the FCS will be appended by the PCnet-

PCI controller regardless of the state of DXMTFCS.

Note that the calculated FCS is transmitted most signifi-

cant bit first. The default value of DXMTFCS is 0 after

H_RESET.

Transmit Exception Conditions

Exception conditions for frame transmission fall into two

distinct categories. Those which are the result of normal

network operation, and those which occur due to abnor-

mal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the PCnet-PCI controller include colli-

sions within the slot time with automatic retry. The

PCnet-PCI controller will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with no

host intervention. The transmit FIFO ensures this by

guaranteeing that data contained within the FIFO will

not be overwritten until at least 64 bytes (512 bits) of pre-

amble plus address, length and data fields have been

transmitted onto the network without encountering

a collision.

If 16 total attempts (initial attempt plus 15 retries) fail, the

PCnet-PCI controller sets the RTRY bit in the current

transmit TDTE in host memory (TMD2), gives up owner-

ship (resets the OWN bit to ZERO) for this frame, and

processes the next frame in the transmit ring for

transmission.

Abnormal network conditions include:

Loss of carrier.

Late collision.

SQE Test Error. (does not apply to 10BASE-T port)

These should not occur on a correctly configured 802.3

network, and will be reported if they do.

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

current descriptor. The OWN bit(s) in the subsequent

descriptor(s) will be reset until the STP (the next frame)

is found.

Loss of Carrier

A loss of carrier condition will be reported if the PCnet-

PCI controller cannot observe receive activity whilst it is

transmitting on the AUI port. After the PCnet-PCI con-

troller initiates a transmission it will expect to see data

“looped-back” on the DI

± pair. This will internally gener-

ate a “carrier sense”, indicating that the integrity of the

data path to and from the MAU is intact, and that the

MAU is operating correctly. This “carrier sense” signal

must be asserted about 6 bit times before the last trans-

mitted bit on DO

±. If “carrier sense” does not become

active in response to the data transmission, or becomes

inactive before the end of transmission, the loss of car-

rier (LCAR) error bit will be set in TMD2 after the frame

has been transmitted. The frame will not be re-tried on

the basis of an LCAR error.

When the 10BASE-T port is selected, LCAR will be re-

ported for every packet transmitted during the Link

fail condition.

Late Collision

A late collision will be reported if a collision condition oc-

curs after one slot time (512 bit times) after the transmit

process was initiated (first bit of preamble commenced).

The PCnet-PCI controller will abandon the transmit

process for the particular frame, set Late Collision

(LCOL) in the associated TMD2, and process the next

transmit frame in the ring. Frames experiencing a late

collision will not be re-tried. Recovery from this condition

must be performed by upper layer software.

SQE Test Error

During the inter packet gap time following the comple-

tion of a transmitted message, the AUI CI

± pair is as-

serted by some transceivers as a self-test. The integral

Manchester Encoder/Decoder will expect the SQE Test

Message (nominal 10 MHz sequence) to be returned via

the CI

± pair, within a 40 network bit time period after DI±

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