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AM79C970 数据表(PDF) 98 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 98 Page - Advanced Micro Devices |
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98 / 168 page  P R E L I M I N A R Y AMD 1-965 Am79C970 CSR32: Next Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXDAL Contains the lower 16 bits of the next TDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR33: Next Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXDAU Contains the upper 16 bits of the next TDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR34: Current Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CXDAL Contains the lower 16 bits of the current TDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR35: Current Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CXDAU Contains the upper 16 bits of the current TDRE address pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR36: Next Next Receive Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NNRDAL Contains the lower 16 bits of the next next receive descriptor ad- dress pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR37: Next Next Receive Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NNRDAU Contains the upper 16 bits of the next next receive descriptor ad- dress pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR38: Next Next Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NNXDAL Contains the lower 16 bits of the next next transmit descriptor ad- dress pointer. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR39: Next Next Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. |
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