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AM79C970 数据表(PDF) 70 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 70 Page - Advanced Micro Devices |
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70 / 168 page  P R E L I M I N A R Y AMD 1-937 Am79C970 Note that accesses to the APROM I/O locations do not directly access the Address EEPROM itself. Instead, these accesses are routed to a set of shadow registers on board the PCnet-PCI controller that are loaded with a copy of the EEPROM contents during the automatic read operation that immediately follows the H_RESET operation. EEPROM MAP The automatic EEPROM read operation will access 18 words (i.e. 36 bytes) of the EEPROM. The format of the EEPROM contents is shown in Table 8, beginning with the byte that resides at the lowest EEPROM address: Table 8. EEPROM Contents EEPROM WORD Byte Byte Address Addr. Most Significant Byte Addr. Least Significant Byte 00h 01h 2nd byte of the ISO 8802-3 00h first byte of the ISO 8802-3 (lowest (IEEE/ANSI 802.3) station physical (IEEE/ANSI 802.3) station physical EEPROM address for this node address for this node, where “first byte” address) refers to the first byte to appear on the 802.3 medium 01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h reserved location: must be 00h 06h reserved location must be 00h 04h 09h Hardware ID: must be 11h if 08h reserved location must be 00h compatibility to AMD drivers is desired 05h 0Bh user programmable space 0Ah user programmable space 06h 0Dh MSByte of two-byte checksum, 0Ch LSByte of two-byte checksum, which is the which is the sum of bytes 00h–0Bh sum of bytes 00h–0Bh and bytes 0Eh and 0Fh and bytes 0Eh and 0Fh 07h 0Fh must be ASCII “W” (57h) if compatibility 0Eh must be ASCII “W” (57h) if compatibility to AMD driver software is desired to AMD driver software is desired 08h 11h BCR16[15:8] (not used) 10h BCR16[7:0] (not used) 09h 13h BCR17[15:8] (not used) 12h BCR17[7:0] (not used) 0Ah 15h BCR18[15:8] (Burst Size and Bus Control) 14h BCR18[7:0] (Burst Size and Bus Control) 0Bh 17h BCR2[15:8] (Misc. configuration) 16h BCR2[7:0] (Misc. configuration) 0Ch 19h BCR21[15:8] (Not Used) 18h BCR21[7:0] (Not Used) 0Dh 1Bh reserved location must be 00h 1Ah reserved location must be 00h 0Eh 1Dh reserved location must be 00h 1Ch reserved location must be 00h 0Fh 1Fh checksum adjust byte for the first 36 bytes 1Eh reserved location must be 00h of the EEPROM contents; checksum of the first 36 bytes of the EEPROM should total to FFh 10h 21h reserved location must be 00h 20h reserved location must be 00h 11h 23h user programmable byte locations 22h user programmable byte locations EEPROM Contents Note that the first bit out of any WORD location in the EEPROM is treated as the MSB of the register that is be- ing programmed. For example, the first bit out of EEPROM WORD location 08h will be written into BCR16[15], the second bit out of EEPROM WORD loca- tion 08h will be written into BCR16[14], etc. There are two checksum locations within the EEPROM. The first is required for the EEPROM address. This checksum will be used by AMD driver software to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station address has not been corrupted. The value of bytes 0Ch and 0Dh should match the sum of bytes 00h through 0Bh and 0Eh and 0Fh. The second checksum location – byte 1Fh – is not a checksum total, but is, instead, a check- sum adjustment. The value of this byte should be such that the total checksum for the entire 36 bytes of EEPROM data equals the value FFh. The checksum ad- just byte is needed by the PCnet-PCI controller in order to verify that the EEPROM contents have not been corrupted. |
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