AM79C970 datasheet(47/168 Pages) AMD

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AMD

P R E L I M I N A R Y

1-914

Am79C970

entry. A device may, however, read from a descriptor

that it does not currently own. Software should always

read descriptor entries in sequential order. When soft-

ware finds that the current descriptor is owned by the

PCnet-PCI controller, then the software must not read

“ahead” to the next descriptor. The software should wait

at the unOWNed descriptor until ownership has been

granted to the software (when SPRINTEN = 1 (CSR3,

bit 5), then this rule is modified. See the SPRINTEN de-

scription). Strict adherence to these rules insures that

“Deadly Embrace” conditions are avoided.

Descriptor Ring Access Mechanism

At initialization, the PCnet-PCI controller reads the base

address of both the transmit and receive descriptor rings

into CSRs for use by the PCnet-PCI controller during

subsequent operations.

As the final step in the self-initialization process, the

base address of each ring is loaded into each of the cur-

rent descriptor address registers and the address of the

next descriptor entry in the transmit and receive rings is

computed and loaded into each of the next descriptor

address registers.

When SSIZE32 = 0, software data structures are 16 bits

wide. The following diagram, Figure 22, illustrates the

relationship between the Initialization Base Address,

the Initialization Block, the Receive and Transmit De-

scriptor Ring Base Addresses, the Receive and Trans-

mit Descriptors and the Receive and Transmit Data

Buffers, for the case of SSIZE32 = 0.

Initialization

Block

24-Bit Base Address

Pointer to

Initialization Block

IADR[15:0]

IADR[23:16]

RES

CSR1

CSR2

TDRA[15:0]

MODE

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLEN

RES

RDRA[23:16]

TLEN

RES

TDRA[23:16]

Rcv

Buffers

RMD0

RMD1 RMD2 RMD3

Rcv Descriptor

Ring

•

1st desc.

start

2nd desc.

start

RMD0

Xmt

Buffers

RX DESCRIPTOR RINGS

TMD0

TMD1

TMD2

TMD3

RX DESCRIPTOR RINGS

Xmt Descriptor

Ring

•

1st desc.

start

2nd desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

18220C-24

Figure 22. 16-Bit Data Structures: Initialization Block and Descriptor Rings

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