AM79C970 datasheet(83/168 Pages) AMD

83 / 168 page

AMD

P R E L I M I N A R Y

1-950

Am79C970

and the PAR lines for a parity er-

ror at the following times:

In slave mode, during the

address phase of any PCI

bus command.

In slave mode, during the

data phase of all I/O and

Configuration Write

commands that select the

PCnet-PCI controller.

In master mode, during the

data phase of all Memory

Read and Memory Read

Line commands.

During the data phase of the

memory write command, the

PCnet-PCI controller sets the

PERR bit if the target reports a

data parity error by asserting the

PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (bit 6 in the Control

PERR is set by the PCnet-PCI

controller and cleared by writing

a ONE. Writing a ZERO has no

effect. PERR is not affected by

H_RESET or S_RESET or as-

serting the

SLEEP pin.

SERR

Signaled SERR. SERR is set

when the PCnet-PCI controller

detects an address parity error,

and both, SERREN and PER-

REN (bits 8 and 6 of the Com-

mand register) are set.

SERR is set by the PCnet-PCI

controller and cleared by writing

a “1”. Writing a “0” has no effect.

SERR is not affected by H_RE-

SET or S_RESET or asserting

the

SLEEP pin.

RMABORT

Received

Master

Abort.

RMABORT is set when the

PCnet-PCI controller terminates

a master cycle with a master

abort sequence.

RMABORT is set by the PCnet-

PCI controller and cleared by

writing a “1”. Writing a “0” has no

effect. RMABORT is not affected

by H_RESET or S_RESET or as-

serting the

SLEEP pin.

RTABORT

Received

Target

Abort.

RTABORT is set when a target

terminates a PCnet-PCI master

cycle

with

target

abort

sequence.

RTABORT is set by the PCnet-

PCI controller and cleared by

writing a “1”. Writing a “0” has no

effect. RTABORT is not affected

by H_RESET or S_RESET or as-

serting the

SLEEP pin.

STABORT

Send Target Abort. STABORT is

set when the PCnet-PCI control-

ler terminates a slave access

with a target abort sequence.

STABORT is set by the PCnet-

PCI controller and cleared by

writing a “1”. Writing a “0” has no

effect. STABORT is not affected

by H_RESET or S_RESET or as-

serting the

SLEEP pin.

10–9 DEVSEL

DEVSEL timing. DEVSEL is set

to 01b (medium), indicating the

PCnet-PCI controller will assert

DEVSEL two CLK periods after

FRAME is asserted.

DEVSEL is read only.

DATAPERR

Data

Parity

Error

detected.

DATAPERR is set when the

PCnet-PCI controller detects a

data parity error during master

mode and the Parity Error Re-

sponse enable bit (bit 6 in the

Control register) is set.

During the data phase of all

Memory Read and Memory Read

Line commands, the PCnet-PCI

controller checks for parity error

by sampling the AD[31:00] and

BE[3:0] and the PAR lines.

During the data phase of all

Memory Write commands, the

PCnet-PCI controller checks the

PERR input to detect whether the

target has reported a parity error.

DATAPERR

set

the

PCnet-PCI

controller

and

cleared by writing a ONE. Writ-

ing a ZERO has no effect.

DATAPERR is not affected by

H_RESET or S_RESET or as-

serting the

SLEEP pin.

7–0

RES

Reserved locations. Read as

ZERO, write operations have no

effect.

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