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AM79C970 数据表(PDF) 94 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 94 Page - Advanced Micro Devices |
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94 / 168 page  P R E L I M I N A R Y AMD 1-961 Am79C970 CSR14: Physical Address Register, PADR[47:32] Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PADR[47:32] Physical Address Register, PADR[47:32]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct I/O write has been per- formed on this register. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR15: Mode Register Bit Name Description This register’s fields are loaded during the PCnet-PCI controller initialization routine with the cor- responding Initialization Block values or a direct I/O write has been performed on this register. 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15 PROM Promiscuous Mode. When PROM = “1”, all incoming receive frames are accepted. Read/write accessible only when STOP bit is set. 14 DRCVBC Disable Receive Broadcast. When set, disables the PCnet- PCI controller from receiving broadcast messages. Used for protocols that do not support broadcast addressing, except as a function of multicast. DRCVBC is cleared by activation of H_RE- SET or S_RESET (broadcast messages will be received) and is unaffected by STOP. Read/write accessible only when STOP bit is set. 13 DRCVPA Disable Receive Physical Ad- dress. When set, the physical ad- dress detection (Station or node ID) of the PCnet-PCI controller will be disabled. Frames addressed to the nodes individ- ual physical address will not be recognized. Read/write accessible only when STOP bit is set. 12 DLNKTST Disable Link Status. When DLNKTST = “1”, monitoring of Link Pulses is disabled. When DLNKTST = “0”, monitoring of Link Pulses is enabled. This pin only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when STOP bit is set. 11 DAPC Disable Automatic Polarity Cor- rection. When DAPC = “1”, the 10BASE-T receive polarity rever- sal algorithm is disabled. Like- wise, when DAPC = “0”, the polarity reversal algorithm is enabled. This bit only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when STOP bit is set. 10 MENDECL MENDEC Loopback Mode. See the description of the LOOP bit in CSR15. Read/write accessible only when STOP bit is set. 9 LRT Low Receive Threshold (T-MAU Mode only) TSEL Transmit Mode Select (AUI Mode only) LRT Low Receive Threshold. When LRT = “1”, the internal twisted pair receive thresholds are re- duced by 4.5 dB below the stan- dard 10BASE-T value (approximately 3/5) and the un- squelch threshold for the RXD circuit will be 180 mV – 312 mV peak. When LRT = “0”, the unsquelch threshold for the RXD circuit will be the standard 10BASE-T value, 300 – 520 mV peak. In either case, the RXD circuit post squelch threshold will be one half of the unsquelch threshold. This bit only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when STOP bit is set. Cleared by H_RESET or S_RESET and is unaffected by STOP. TSEL Transmit Mode Select. TSEL controls the levels at which the |
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