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AM79C970 数据表(PDF) 91 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 91 Page - Advanced Micro Devices |
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91 / 168 page  AMD P R E L I M I N A R Y 1-958 Am79C970 the Runt Packet Accept (RPA) bit (CSR124, bit 3) may be changed only when ENTST is set to ONE. To enable RPA, the user must first write a ONE to the ENTST bit. Next, the user must first write a ONE to the RPA bit (CSR124, bit 3). Finally, the user must write a ZERO to the ENTST bit to take the device out of test mode op- eration. Once, the RPA bit has been set to ONE, the device will remain in the Runt Packet Accept mode until the RPA bit is cleared to ZERO. Read/Write accessible. ENTST is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 14 DMAPLUS When DMAPLUS = “1”, DMA Burst Counter in CSR80 is dis- abled. If DMAPLUS = “0”, the counter is enabled. Read/Write accessible. DMAPLUS is cleared by H_RE- SET or S_RESET and is unaf- fected by the STOP bit. 13 TIMER Timer Enable Register. If TIMER is set, the Bus Timer Register, CSR82 is enabled. If TIMER is cleared, the Bus Timer Register is disabled. Read/Write accessible. TIMER is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 12 DPOLL Disable Transmit Polling. If DPOLL is set, the Buffer Man- agement Unit will disable trans- mit polling. Likewise, if DPOLL is cleared, automatic transmit poll- ing is enabled. If DPOLL is set, TDMD bit in CSR0 must be set in order to initiate a manual poll of a transmit descriptor. Transmit de- scriptor polling will not take place if TXON is reset. Read/Write accessible. DPOLL is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 11 APAD_XMT Auto Pad Transmit. When set, APAD_XMT enables the auto- matic padding feature. Transmit frames will be padded to extend them to 64 bytes including FCS. The FCS is calculated for the en- tire frame including pad, and ap- pended after the pad field. APAD_XMT will override the pro- gramming of the DXMTFCS bit. Read/Write accessible. APAD_XMT is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 10 ASTRP_RCV Auto Strip Receive. When set, ASTRP_RCV enables the auto- matic pad stripping feature. The pad and FCS fields will be stripped from receive frames and not placed in the FIFO. Read/Write accessible. ASTRP_RCV is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 9 MFCO Missed Frame Counter Overflow Interrupt. Indicates the MFC (CSR112) wrapped around. Can be cleared by writing a 1 to this bit. Also cleared by H_RESET, S_RESET or by asserting the STOP bit. Writing a 0 has no effect. When MFCO is set, INTA is as- serted if IENA is ONE and the mask bit MFCOM is ZERO. When the value 01h has been programmed into the SWSTYLE register (BCR20, bits 7–0) for ILACC (Am79C900) compatibil- ity, then this bit has no meaning and PCnet-PCI controller will never set the value of this bit to ONE. 8 MFCOM Missed Frame Counter Overflow Mask. If MFCOM is set, MFCO will be unable to set INTR in CSR0. Set to a ONE by H_RESET or S_RESET, unaffected by the STOP bit. When the value 01h has been programmed into the SWSTYLE register (BCR20, bits 7–0) for ILACC (Am79C900) compatibil- ity, then this bit has no meaning and PCnet-PCI controller will set the value of this bit to ZERO. 7 RES Reserved location. Written as ZERO and read as ZERO. 6 RES Reserved location. This bit may be written to as either a ONE or a ZERO, but will always be read as a ZERO. This bit has no effect on PCnet-PCI controller operation. 5 RCVCCO Receive Collision Counter Overflow. Indicates the Receive Collision Counter (CSR114) wrapped around. Can be cleared by |
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