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AM79C970 数据表(PDF) 74 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 74 Page - Advanced Micro Devices |
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74 / 168 page ![]() P R E L I M I N A R Y AMD 1-941 Am79C970 Note that for some network protocols, the value passed in the Ethernet Type and/or 802.3 Length field is not compliant with either standard and may cause problems. Figure 28 shows the byte/bit ordering of the received length field for an 802.3 compatible frame format. Preamble 1010....1010 Sync 10101011 Destination Address Source Address Length LLC Data Pad FCS 4 Bytes 46 — 1500 Bytes 2 Bytes 6 Bytes 6 Bytes 8 Bits 56 Bits Start of Frame at Time = 0 Increasing Time Bit 0 Bit 7 Bit 0 Bit 7 Most Significant Byte Least Significant Byte 1 — 1500 Bytes 45 — 0 Bytes 18220C-30 Figure 28. 802.3 Frame and Length Field Transmission Order Receive FCS Checking Reception and checking of the received FCS is per- formed automatically by the PCnet-PCI controller. Note that if the Automatic Pad Stripping feature is enabled, the FCS for padded frames will be verified against the value computed for the incoming bit stream including pad characters, but the FCS value for a padded frame will not be passed to the host. If an FCS error is detected in any frame, the error will be reported in the CRC bit in RMD1. Receive Exception Conditions Exception conditions for frame reception fall into two distinct categories; those which are the result of normal network operation, and those which occur due to abnor- mal network and/or host related events. Normal events which may occur and which are handled autonomously by the PCnet-PCI controller are basically collisions within the slot time and automatic runt packet rejection. The PCnet-PCI controller will ensure that colli- sions which occur within 512 bit times from the start of reception (excluding preamble) will be automatically de- leted from the receive FIFO with no host intervention. The receive FIFO will delete any frame which is com- posed of fewer than 64 bytes provided that the Runt Packet Accept (RPA bit in CSR124) feature has not been enabled. This criterion will be met regardless of whether the receive frame was the first (or only) frame in the FIFO or if the receive frame was queued behind a previously received message. Abnormal network conditions include: FCS errors Late Collision Host related receive exception conditions include MISS, BUFF, and OFLO. These are described in the BMU section. Loopback Operation Loopback is a mode of operation intended for system di- agnostics. In this mode, the transmitter and receiver are both operating at the same time so that the controller re- ceives its own transmissions. The controller provides two types of internal loopback and one type of external loopback. In internal loopback mode, the transmitted data can be looped back to the receiver at one of two places inside the controller without actually transmitting any data to the external network. The receiver will move the received data to the next receive buffer, where it can be examined by software. Alternatively, in external loop- |
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