AM79C970 datasheet(85/168 Pages) AMD

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AMD

P R E L I M I N A R Y

1-952

Am79C970

RES

Reserved

location.

Read

ZERO, write operations have no

effect.

IOSPACE

I/O space indicator. Read as

ONE, write operations have no

effect. Indicating that this Base

Address register describes an

I/O base address.

Interrupt Line Register (Offset 3Ch)

The Interrupt Line register is an 8-bit register that is used

to communicate the routing of the interrupt. This register

is written by the POST software as it initialized the

PCnet-PCI controller in the system. The register is read

by the network driver to determine the interrupt channel

which the POST software has assigned to the PCnet-

PCI controller. The Interrupt Line register is not modified

by the PCnet-PCI controller. It has no effect on the op-

eration of the device.

The Interrupt Line register is located at offset 3Ch in the

PCI Configuration Space. It is read an written by the

host. It is not effected by H_RESET or S_RESET or as-

serting the

SLEEP pin.

Interrupt Pin Register (Offset 3Dh)

This Interrupt Pin register is an 8-bit register indicating

the interrupt pin the PCnet-PCI controller is using. The

value for the PCnet-PCI Interrupt Pin register is 01h,

which corresponds to INTA.

The Interrupt Pin register is located at offset 3Dh in the

PCI Configuration Space. It is read only.

RAP Register

The RAP (Register Address Pointer) register is used to

gain access to CSR and BCR registers on board the

PCnet-PCI controller. The value of the RAP indicates

the address of a CSR or BCR whenever an RDP or BDP

access is performed. That is to say, RAP serves as a

pointer to CSR and BDP space.

As an example of RAP use, consider a read access to

CSR4. In order to access this register, it is necessary to

first load the value 0004h into the RAP by performing a

write access to the RAP offset of 12h (12h when WIO

mode has been selected, 14h when DWIO mode has

been selected). Then a second access is performed

PCnet-PCI controller, this time to the RDP offset of 10h

(for either WIO or DWIO mode). The RDP access is a

read access, and since RAP has just been loaded with

the value of 0004h, the RDP read will yield the contents

of CSR4. A read of the BDP at this time (offset of 16h

when WIO mode has been selected, 1Ch when DWIO

mode has been selected) will yield the contents of

BCR4, since the RAP is used as the pointer into both

BDP and RDP space.

RAP: Register Address Port

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–8

RES

Reserved locations. Read and

written as ZEROs.

7–0

RAP

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP port, respectively, is

performed.

A write access to undefined CSR

or BCR locations may cause un-

expected reprogramming of the

PCnet-PCI control registers. A

read access will yield undefined

values.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

the STOP bit.

Control and Status Registers

The CSR space is accessible by performing accesses to

the RDP (Register Data Port). The particular CSR that is

read or written during an RDP access will depend upon

the current setting of the RAP. RAP serves as a pointer

into the CSR space. RAP also serves as the pointer to

BCR space, which is described in a later section.

CSR0: PCnet-PCI Controller Status Register

Bit

Name

Description

Certain bits in CSR0 indicate the

cause of an interrupt. The regis-

ter is designed so that these indi-

cator bits are cleared by writing

ONEs to those bit locations. This

means that the software can read

CSR0 and write back the value

just read to clear the interrupt

condition.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

ERR

Error is set by the ORing of

BABL, CERR, MISS, and MERR.

ERR remains set as long as any

of the error flags are true. ERR is

read only. Write operations are

ignored.

BABL

Babble is a transmitter time-out

error. It indicates that the trans-

mitter has been on the channel

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