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AM79C970 数据表(PDF) 96 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 96 Page - Advanced Micro Devices |
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96 / 168 page  P R E L I M I N A R Y AMD 1-963 Am79C970 and therefore no transmissions are attempted. DTX = “0”, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read/write accessible only when STOP bit is set. 0 DRX Disable Receiver results in PCnet-PCI controller not access- ing the Receive Descriptor Ring and therefore all receive frame data are ignored. DRX = “0”, will set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. Read/write accessible only when STOP bit is set. CSR16: Initialization Block Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 IADR[15:0] This register is an alias of CSR1. CSR17: Initialization Block Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0IADR[31:16] This register is an alias of CSR2. CSR18: Current Receive Buffer Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CRBAL Contains the lower 16 bits of the current receive buffer address at which the PCnet-PCI controller will store incoming frame data. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR19: Current Receive Buffer Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CRBAU Contains the upper 16 bits of the current receive buffer address at which the PCnet-PCI controller will store incoming frame data. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR20: Current Transmit Buffer Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CXBAL Contains the lower 16 bits of the current transmit buffer address from which the PCnet-PCI con- troller is transmitting. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR21: Current Transmit Buffer Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CXBAU Contains the upper 16 bits of the current transmit buffer address from which the PCnet-PCI con- troller is transmitting. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR22: Next Receive Buffer Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRBAL Contains the lower 16 bits of the next receive buffer address to which the PCnet-PCI controller will store incoming frame data. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR23: Next Receive Buffer Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRBAU Contains the upper 16 bits of the next receive buffer address to which the PCnet-PCI controller will store incoming frame data. |
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