AM79C970 datasheet(86/168 Pages) AMD

86 / 168 page

P R E L I M I N A R Y

AMD

1-953

Am79C970

longer than the time required to

send the maximum length frame.

BABL will be set if 1519 bytes or

greater are transmitted.

When BABL is set,

INTA is as-

serted if IENA = 1 and the mask

bit BABLM in CSR3 is clear.

BABL assertion will set the ERR

bit.

BABL is set by the MAC layer and

cleared by writing a “1”. Writing a

“0” has no effect. BABL is cleared

by H_RESET or S_RESET or by

setting the STOP bit.

CERR

Collision Error indicates that the

collision inputs to the AUI port

failed to activate within 20 net-

work bit times after the chip ter-

minated

transmission

(SQE

Test). This feature is a trans-

ceiver test feature.

In 10BASE-T mode, CERR will

be set after a transmission if the

T-MAU is in link fail state.

CERR assertion will not result in

an interrupt being generated.

CERR assertion will set the ERR

bit.

CERR is set by the MAC layer

and cleared by writing a “1”. Writ-

ing a “0” has no effect. CERR is

cleared by H_RESET or S_RE-

SET or by setting the STOP bit.

MISS

Missed

Frame

set

when

PCnet-PCI controller has lost an

incoming receive frame resulting

from a Receive Descriptor not

being available. This bit is the

only immediate indication that re-

ceive data has been lost since

there is no current receive de-

scriptor. Missed Frame Counter

(CSR112) also increments each

time a receive frame is missed.

When MISS is set,

INTA is as-

serted if IENA = 1 and the mask

bit MISSM in CSR3 is clear.

MISS assertion will set the ERR

bit.

MISS is set by the Buffer Man-

agement Unit and cleared by

writing a “1”. Writing a “0” has no

effect. MISS is cleared by H_RE-

SET or S_RESET or by setting

the STOP bit.

MERR

Memory Error is set when PCnet-

PCI controller requests the use of

the system interface bus by as-

serting

REQ

and

has

not

received

GNT assertion after a

programmable length of time.

The length of time in microsec-

onds before MERR is asserted

will depend upon the setting of

the

Bus

Timeout

(CSR100). The default setting of

CSR100 will give a MERR after

51.2

microseconds

bus

latency.

When MERR is set,

INTA is as-

serted if IENA = 1 and the mask

bit MERRM in CSR3 is clear.

MERR assertion will set the ERR

bit, regardless of the settings of

IENA and MERRM.

MERR is set by the Bus Interface

Unit and cleared by writing a “1”.

Writing a “0” has no effect. MERR

cleared

H_RESET,

S_RESET or by setting the

STOP bit.

RINT

Receive Interrupt. RINT is set by

the Buffer Management Unit of

the PCnet-PCI controller after

the last descriptor of a receive

packet has been updated by writ-

ing a ZERO to the ownership bit.

RINT may also be set when the

first descriptor of a receive pack-

et has been updated by writing a

ZERO to the ownership bit if the

SPRINTEN bit of CSR3 has been

set to a ONE.

When RINT is set,

INTA is as-

serted if IENA = 1 and the mask

bit RINTM in CSR3 is clear.

RINT is cleared by the host by

writing a “1”. Writing a “0” has no

effect.

RINT is cleared by

H_RESET, S_RESET or by set-

ting the STOP bit.

TINT

Transmit Interrupt is set after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

sent or an error occurred in the

transmission.

When TINT is set,

INTA is as-

serted if IENA = 1 and the mask

bit TINTM in CSR3 is clear.

TINT is set by the Buffer Man-

agement Unit and cleared by

writing a “1”. Writing a “0” has no

effect.

TINT

cleared

H_RESET or S_RESET or by

setting the STOP bit.

IDON

Initialization Done indicates that

the initialization sequence has

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