AM79C970 datasheet(42/168 Pages) AMD

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P R E L I M I N A R Y

AMD

1-909

Am79C970

Slave I/O Transfers

After the PCnet-PCI controller is configured as I/O de-

vice (by setting IOEN in the PCI Command register), it

starts monitoring the PCI bus for access to its internal

registers. The PCnet-PCI controller will look for an ad-

dress that falls within its 32 bytes of I/O address space

(starting from the I/O base address). The PCnet-PCI

controller will assert

DEVSEL if it detects an address

match and the access is an I/O cycle.

DEVSEL is as-

serted two clock cycles after the host has asserted

FRAME. The PCnet-PCI controller will not assert DEV-

SEL if it detects an address match, but the PCI com-

mand is not of the type I/O read or I/O write. The

PCnet-PCI controller will suspend looking for I/O cycles

while being a bus master.

Slave I/O Read

The Slave I/O Read command is used by the host CPU

to read the PCnet-PCI’s CSRs, BCRs and EEPROM lo-

cations. It is a single cycle, non-burst 8-bit,16-bit or

32-bit transfer which is initiated by the host CPU. The

typical number of wait states added to a slave I/O read

access on the part of the PCnet-PCI controller is 6 to 7

clock cycles, depending upon the relative phases of the

internal Buffer Management Unit clock and the CLK sig-

nal, since the internal Buffer Management Unit clock is a

divide-by-two version of the CLK signal. The PCnet-PCI

controller will not produce Slave I/O Read commands

while being a bus master.

FRAME

CLK

IRDY

TRDY

12345678

ADDR

DATA

0010

BE's

910

PAR

STOP

DEVSEL

18220C-20

Figure 18. Slave I/O Read

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