AM79C970 datasheet(62/168 Pages) AMD

62 / 168 page

P R E L I M I N A R Y

AMD

1-929

Am79C970

Device ID

Vendor ID

00h

Status

Command

04h

Base-Class

Sub-Class

Programming IF

Revision ID

08h

Reserved

Header Type

Latency Timer

Reserved

0Ch

Base Address

10h

Reserved

14h

Reserved

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Reserved

2Ch

Reserved

30h

Reserved

34h

Reserved

38h

Reserved

Interrupt Pin

Interrupt Line

3Ch

24 23

16 15

Offset

The configuration registers are accessible only by PCI

configuration cycles. They can be accessed right after

the PCnet-PCI controller is powered-on, even if the read

operation of the serial EEPROM is still on-going. All

multi-byte numeric fields follow little endian byte order-

ing. The Command register is the only register cleared

by H_RESET. S_RESET as well as asserting

SLEEP

have no effect on the value of the PCI configuration reg-

isters. All write accesses to Reserved locations have no

effect, reads from these locations will return a data value

of ZERO.

When the PCnet-PCI controller samples its IDSEL input

asserted during a configuration cycle, it will acknowl-

edge the cycle by asserting its

DEVSEL output. The

content of AD[31:00] during the address phase of the

configuration cycles must meet the format as shown

below:

Don’t

Don’t Care

Care

0 0

DWORD Index

0 0

11 10

8 7

6 5

2 1 0

AD[1:0] must both be ZEROs, since the PCnet-PCI con-

troller is not a bridge device. It only recognizes configu-

ration cycles of Type 0 (as defined by the PCI

specification revision 2.0). AD[7:2] specify the selected

DWORD in the configuration space. AD[7:6] must both

be ZERO, since the PCnet-PCI controller does not im-

plement any of the device specific registers in locations

64 – 255. Since AD[1:0] and AD[7:6] must all be ZERO,

the lower 8 bits of the address for a configuration cycle

are equal to the offset of the DWORD counting from the

beginning of the PCI configuration space. AD[10:8]

specify one of eight possible functions of a PCI device.

The PCnet-PCI controller is a single function device, as

indicated in the Header Type register of its PCI configu-

ration space (bit 7, FUNCT = 0). Therefore, the PCnet-

PCI controller ignores AD[10:8] during the address

phase of a configuration cycle. AD[31:11] are typically

used to generate the IDSEL signal. The PCnet-PCI con-

troller ignores all upper address bits.

PCI configuration registers can be accessed with 8-bit,

16-bit or 32-bit transfers. The active bytes within a

DWORD are determined by the byte enable signals.

E.G. a read of the Sub-Class register can be performed

by reading from offset 08h with only

BE2 being active.

I/O Resources

PCnet-PCI Controller I/O Resource Mapping

The PCnet-PCI controller has several I/O resources.

These resources use 32 bytes of I/O space that begin at

the PCnet-PCI controller I/O base address.

The PCnet-PCI controller allows two modes of slave ac-

cess. Word I/O mode treats all PCnet-PCI controller I/O

Resources as two-byte entities spaced at two-byte ad-

dress intervals. Double Word I/O mode treats all PCnet-

PCI controller I/O Resources as four-byte entities

spaced at four-byte address intervals. The selection of

WIO or DWIO mode is accomplished by one of

two ways:

H_RESET function.

Automatic determination of DWIO mode due to

DWORD (double-word) I/O write access to offset

10h.

The PCnet-PCI controller I/O mode setting will default to

WIO after H_RESET (i.e. DWIO = 0).

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