AM79C970 datasheet(82/168 Pages) AMD

82 / 168 page

P R E L I M I N A R Y

AMD

1-949

Am79C970

Command Register (offset 04h)

The Command register is a 16-bit register used to con-

trol the gross functionality of the PCnet-PCI controller. It

controls the PCnet-PCI controller’s ability to generate

and respond to PCI bus cycles. To logically disconnect

the PCnet-PCI device from all PCI bus cycles except

Configuration cycles, a value of ZERO should be written

to this register.

The Command register is located at offset 04h in the PCI

Configuration Space. It is read and written by the host.

15-10

RES

Reserved locations. Read as

ZERO, write operations have no

effect.

FBTBEN

Fast Back-to-Back enable. Read

as ZERO, write operations have

no effect. The PCnet-PCI con-

troller will not generate Fast

Back-to-Back cycles.

SERREN

SERR enable. Controls the as-

sertion of the

SERR pin. SERR is

disabled

when

SERREN

cleared.

SERR will be asserted

on detection of an address parity

error and if both, SERREN and

PERREN (bit 6 of this register)

are set.

SERREN is cleared by H_RE-

SET and is not effected by

S_RESET

asserting

the

SLEEP pin.

ADSTEP

Address/data stepping. Read as

ONE, write operations have no

effect. The PCnet-PCI controller

uses address stepping for the

first address phase of each bus

master period.

FRAME will be

asserted on the second CLK fol-

lowing the assertion of

GNT indi-

cating a valid address on the

AD bus.

PERREN

Parity Error Response enable.

Enables the parity error re-

sponse functions. When PER-

REN is ‘0’ and the PCnet-PCI

controller detects a parity error, it

only sets the Detected Parity Er-

ror bit in the Status register.

When PERREN is ‘1’, the PCnet-

PCI controller asserts

PERR on

the detection of a data parity er-

ror. It also sets the DATAPERR

bit (bit 8 in the Status register),

when the data parity error oc-

curred during a master cycle.

PERREN also enables reporting

address parity errors through the

SERR pin and the SERR bit in

the Status register.

PERREN

cleared

H_RESET and is not effected by

S_RESET

asserting

the

SLEEP pin.

VGASNOOP

VGA palette snoop. Read as

ZERO, write operations have no

effect.

MWIEN

Memory Write and Invalidate Cy-

cle enable. Read as ZERO, write

operations have no effect. The

PCnet-PCI controller only gener-

ates Memory Write cycles.

SCYCEN

Special Cycle enable. Read as

ZERO, write operations have no

effect. The PCnet-PCI controller

ignores

all

Special

Cycle

operations.

BMEN

Bus

Master

enable.

Setting

BMEN enables the PCnet-PCI

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

bit in CSR0 of the PCnet-PCI

controller. (Setting INIT causes

the PCnet-PCI controller to start

its first bus master operation,

which is reading in the initializa-

tion block.)

BMEN is cleared by H_RESET

and is not effected by S_RESET

or asserting the

SLEEP pin.

MEMEN

Memory Space access enable.

Read as ZERO, write operations

have no effect. The PCnet-PCI

controller

has

memory

mapped resources.

IOEN

I/O Space access enable. The

PCnet-PCI controller will ignore

all I/O accesses when IOEN is

cleared. The host must set IOEN

before the first I/O access to the

device. The Base Address regis-

ter at offset 10h must be pro-

grammed

with

valid

I/O

address before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or asserting the

SLEEP pin.

Status Register (Offset 06h)

The Status register is a 16-bit register that contains

status information for the PCI bus related events. It is lo-

cated at offset 06h in the PCI Configuration Space.

PERR

Parity Error. PERR is set when

the PCnet-PCI controller detects

a parity error.

The PCnet-PCI controller sam-

ples the AD[31:00], C/

BE[3:0]

AM79C970 数据表(PDF) 82 Page - Advanced Micro Devices

AM79C970 数据表(HTML) 82 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C970 数据表(PDF) 82 Page - Advanced Micro Devices

AM79C970 数据表(HTML) 82 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载