AM79C970 datasheet(56/168 Pages) AMD

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AMD

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Am79C970

Transmission is enabled by the controller. As long as the

ITXEN request remains active, the serial output of the

controller will be Manchester encoded and appear at

±. When the internal request is dropped by the con-

troller, the differential transmit outputs go to one of two

idle states, dependent on TSEL in the Mode Register

(CSR15, bit 9):

TSEL LOW:

The idle state of DO

± yields “ZERO”

differential to operate transformer-

coupled loads.

TSEL HIGH: In this idle state, DO+ is positive with

respect to DO– (logical HIGH).

Receiver Path

The principal functions of the Receiver are to signal the

PCnet-PCI controller that there is information on the re-

ceive pair, and separate the incoming Manchester en-

coded data stream into clock and NRZ data.

The Receiver section (see Receiver Block Diagram)

consists of two parallel paths. The receive data path is a

ZERO threshold, wide bandwidth line receiver. The car-

rier path is an offset threshold bandpass detecting line

receiver. Both receivers share common bias networks

to allow operation over a wide input common

mode range.

18220C-26

Noise

Reject

Filter

Data

Receiver

Carrier

Detect

Circuit

Manchester

Decoder

IRXDAT*

ISRDCLK*

IRXCRS*

*Internal signal

Figure 24. Receiver Block Diagram

Input Signal Conditioning

Transient noise pulses at the input data stream are re-

jected by the Noise Rejection Filter. Pulse width rejec-

tion is proportional to transmit data rate.

The Carrier Detection circuitry detects the presence of

an incoming data frame by discerning and rejecting

noise from expected Manchester data, and controls the

stop and start of the phase-lock loop during clock acqui-

sition. Clock acquisition requires a valid Manchester bit

pattern of 1010b to lock onto the incoming message.

When input amplitude and pulse width conditions are

met at DI

±, the internal enable signal from the MENDEC

to controller (IRXCRS) is asserted and a clock acquisi-

tion cycle is initiated.

Clock Acquisition

When there is no activity at DI

± (receiver is idle), the re-

ceive oscillator is phase locked to internal transmit

clock. The first negative clock transition (bit cell center of

first valid Manchester “0”) after IRXCRS is asserted in-

terrupts the receive oscillator. The oscillator is then re-

started at the second Manchester “0” (bit time 4) and is

phase locked to it. As a result, the MENDEC acquires

the clock from the incoming Manchester bit pattern in

4 bit times with a 1010b Manchester bit pattern.

ISRDCLK and IRXDAT are enabled 1/4 bit time after

clock acquisition in bit cell 5. IRXDAT is at a HIGH state

when the receiver is idle (no ISRDCLK). IRXDAT how-

ever, is undefined when clock is acquired and may re-

main HIGH or change to LOW state whenever

ISRDCLK is enabled. At 1/4 bit time through bit cell 5,

the controller portion of the PCnet-PCI controller sees

the first ISRDCLK transition. This also strobes in the in-

coming fifth bit to the MENDEC as Manchester “1”.

IRXDAT may make a transition after the ISRDCLK rising

edge in bit cell 5, but its state is still undefined. The

Manchester “1” at bit 5 is clocked to IRXDAT output at

1/4 bit time in bit cell 6.

PLL Tracking

After clock acquisition, the phase-locked clock is com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a cor-

rection circuit. This circuit ensures that the phase-

locked clock remains locked on the received signal.

Individual bit cell phase corrections of the Voltage Con-

trolled Oscillator (VCO) are limited to 100% of the phase

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