AM79C970 datasheet(90/168 Pages) AMD

90 / 168 page

P R E L I M I N A R Y

AMD

1-957

Am79C970

will always be written to a sepa-

rate memory area. The interrupt

is generated when the “header”

bytes have been written to the

“header” memory area.

Read/Write accessible always.

The LAPPEN bit will be reset to

ZERO

H_RESET

S_RESET and will be unaffected

by STOP.

See Appendix D for more infor-

mation on the LAPP concept.

DXMT2PD

Disable Transmit Two Part De-

ferral (see Medium Allocation

section in Media Access Man-

agement fro more details). If

DXMT2PD is set, Transmit Two

Part Deferral will be disabled.

Read/Write accessible always.

DXMT2PD is cleared by H_RE-

SET or S_RESET and is not af-

fected by STOP.

EMBA

Enable Modified Back-off Algo-

rithm (see Contention Resolution

section in Media Access Man-

agement for more details). If

EMBA is set, a modified back-off

algorithm is implemented.

Read/Write accessible always.

EMBA is cleared by H_RESET or

S_RESET and is not affected by

STOP.

BSWP

Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a ONE, big En-

dian mode is selected. When

BSWP is set to ZERO, little En-

dian mode is selected.

When big Endian mode is se-

lected, the PCnet-PCI controller

will swap the order of bytes on

the AD bus during a data phase

on accesses to the FIFOs only.

Specifically, AD[31:24] becomes

BYTE0,

AD[23:16]

becomes

BYTE1,

AD[15:8]

becomes

BYTE2 and AD[7:0] becomes

BYTE3 when big Endian mode is

selected.

When

little

Endian

mode is selected, the order of

bytes on the AD bus during a data

phase is: AD[31:24] is BYTE3,

AD[23:16] is BYTE2, AD[15:8] is

BYTE1 and AD[7:0] is BYTE0.

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

BSWP bit. Descriptor transfers

are not affected by the setting of

the BSWP bit. RDP, RAP and

BDP accesses are not affected

by the setting of the BSWP bit.

APROM transfers are not af-

fected by the setting of the BSWP

bit.

Note that the byte ordering of the

PCI bus is defined to be little en-

dian. BSWP must not be set to

ONE when the PCnet-PCI con-

troller operates in a PCI system.

BSWP is write/readable regard-

less of the state of the STOP bit.

BSWP is cleared by H_RESET

or S_RESET and is not affected

by STOP bit.

RES

Reserved location. The default

value of this bit is a ZERO. Writ-

ing a ONE to this bit has no effect

on device function; If a ONE is

written to this bit, then a ONE will

be read back. Existing drivers

may write a ONE to this bit for

compatibility, but new drivers

should write a ZERO to this bit

and should treat the read value

as undefined.

RES

Reserved location. The default

value of this bit is a ZERO. Writ-

ing a ONE to this bit has no effect

on device function. If a ONE is

written to this bit, then a ONE will

be read back. Existing drivers

may write a ONE to this bit for

compatibility, but new drivers

should write a ZERO to this bit

and should treat the read value

as undefined.

CSR4: Test and Features Control

Bit

Name

Description

Certain bits in CSR4 indicate the

cause of an interrupt. The regis-

ter is designed so that these indi-

cator bits are cleared by writing

ONEs to those bit locations. This

means that the software can read

CSR4 and write back the value

just read to clear the interrupt

condition.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

ENTST

Enable Test Mode operation.

Setting ENTST to ONE enables

internal test functions which are

useful only for stand alone inte-

grated circuit testing. In addition,

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