AM79C970 datasheet(54/168 Pages) AMD

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P R E L I M I N A R Y

AMD

1-921

Am79C970

sequence before ceasing transmission and invoking the

random backoff algorithm.

This transmit two part deferral algorithm is implemented

as an option which can be disabled using the DXMT2PD

bit in CSR3. Two part deferral after transmission is use-

ful for ensuring that severe IPG shrinkage cannot occur

in specific circumstances, causing a transmit message

to follow a receive message so closely as to make them

indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device), should gen-

erate the SQE Test message (a nominal 10 MHz burst of

5 –15 Bit Times duration) on the CI

± pair (within 0.6 µs –

1.6

µs after the transmission ceases). During the time

period in which the SQE Test message is expected the

PCnet-PCI controller will not respond to receive

carrier sense.

See ANSI/IEEE Std 802.3—1990 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the DTE opens

a time window during which it expects to see the sig-

nal_quality_error

signal asserted on the Control In cir-

cuit.

The

time

window

begins

when

the

CARRIER_STATUS becomes CARRIER_OFF. If exe-

cution of the output function does not cause CAR-

RIER_ON to occur, no SQE test occurs in the DTE. The

duration of the window shall be at least 4.0

µs but no

more than 8.0

µs. During the time window the Carrier

Sense Function is inhibited.”

The PCnet-PCI controller implements a carrier sense

“blinding” period within 0

µs – 4.0 µs from de-assertion

of carrier sense after transmission. This effectively

means that when transmit two part deferral is enabled

(DXMT2PD is cleared) the IFS1 time is from 4

µs to 6 µs

after a transmission. However, since IPG shrinkage be-

low 4

µs will rarely be encountered on a correctly config-

ured networks, and since the fragment size will be larger

than the 4

µs blinding window, then the IPG counter will

be reset by a worst case IPG shrinkage/fragment sce-

nario and the PCnet-PCI controller will defer its trans-

mission. In addition, the PCnet-PCI controller will not

restart the “blinding” period if carrier is detected within

the 4.0

µs – 6.0 µs IFS1 period, but will commence tim-

ing of the entire IFS1 period.

Contention Resolution (Collision Handling)

Collision detection is performed and reported to the

MAC engine by the integrated Manchester Encoder/De-

coder (MENDEC). If a collision is detected before the

complete preamble/SFD sequence has been transmit-

ted, the MAC Engine will complete the preamble/SFD

before appending the jam sequence. If a collision is de-

tected after the preamble/SFD has been completed, but

prior to 512 bits being transmitted, the MAC Engine will

abort the transmission, and append the jam sequence

immediately. The jam sequence is a 32-bit all Zeros

pattern.

The MAC Engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be re-scheduled, de-

pendent on the backoff time that the MAC Engine

computes. If a single retry was required, the ONE bit will

be set in the Transmit Frame Status. If more than one

retry was required, the MORE bit will be set. If all 16 at-

tempts experienced collisions, the RTRY bit will be set

(ONE and MORE will be clear), and the transmit mes-

sage will be flushed from the FIFO. If retries have been

disabled by setting the DRTY bit in CSR15, the MAC En-

gine will abandon transmission of the frame on detection

of the first collision. In this case, only the RTRY bit will be

set and the transmit message will be flushed from

the FIFO.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MAC Engine will abort the transmission, append the jam

sequence and set the LCOL bit. No retry attempt will be

scheduled on detection of a late collision, and the trans-

mit message will be flushed from the FIFO.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires

use of a “truncated binary exponential backoff” algo-

rithm which provides a controlled pseudo random

mechanism to enforce the collision backoff interval, be-

fore re-transmission is attempted.

See ANSI/IEEE Std 802.3—1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA/CD sublayer delays before attempting to re-

transmit the frame. The delay is an integer multiple of

slot Time. The number of slot times to delay before the

nth re-transmission attempt is chosen as a uniformly

distributed random integer r in the range:

≤ r <2k

where

k = min (n,10).”

The PCnet-PCI controller provides an alternative algo-

rithm, which suspends the counting of the slot time/IPG

during the time that receive carrier sense is detected.

This aids in networks where large numbers of nodes are

present, and numerous nodes can be in collision. It ef-

fectively accelerates the increase in the backoff time in

busy networks, and allows nodes not involved in the col-

lision to access the channel whilst the colliding nodes

await a reduction in channel activity. Once channel ac-

tivity is reduced, the nodes resolving the collision time

out their slot time counters as normal.

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