AM79C970 datasheet(65/168 Pages) AMD

65 / 168 page

AMD

P R E L I M I N A R Y

1-932

Am79C970

APROM Access

The APROM space is a convenient place to store the

value of the 48-bit IEEE station address. This space is

automatically loaded from the serial EEPROM, if an

EEPROM is present. It can be overwritten by the host

computer. Its contents have no effect on the operation of

the controller. The software must copy the station ad-

dress from the APROM space to the initialization block

or to CSR12-14 in order for the receiver to accept

unicast frames directed to this station.

When programmed for WIO mode, any byte or word ad-

dress from an offset of 0h to an offset of Fh may be read.

An appropriate byte or word of APROM contents will be

delivered by the PCnet-PCI controller in response to ac-

cesses that fall within the APROM range of 0h to Fh.

When programmed for DWIO mode, only DWORD ad-

dresses from an offset of 0h to an offset of Fh may be

read. An appropriate DWORD of APROM contents will

be delivered in response to accesses that fall within the

APROM range of 0h to Fh.

Accesses of non-DWORD

quantities are not allowed in

DWIO mode, even though such an access may be prop-

erly aligned to a DWORD address boundary.

Write access to any of the APROM locations is allowed,

but only 4 bytes on DWORD boundaries in DWIO mode

or 2 bytes on word boundaries in WIO mode (only read

accesses to the APROM locations can be in 8-bit quanti-

ties while in WIO mode). The IESRWE bit (see BCR2)

must be set in order to enable a write operation to the

APROM. Only the PCnet-PCI controller on-board IEEE

Shadow registers are modified by writes to APROM lo-

cations. The EEPROM is unaffected by writes to

APROM locations.

Note that the APROM locations occupy 16 bytes of

space, yet the IEEE station address requirement is for 6

bytes. The 6 bytes of IEEE station address occupy the

first 6 locations of the APROM space. The next six bytes

are reserved. Bytes 12 and 13 should match the value of

the checksum of bytes 1 through 11 and 14 and 15.

Bytes 14 and 15 should each be ASCII W (57h). The

above requirements must be met in order to be compat-

ible with AMD driver software.

RDP Access (CSR Register Space)

RDP = Register Data Port. The RDP is used with the

RAP to gain access to any of the PCnet-PCI controller

CSR locations.

Access to any of the CSR locations of the PCnet-PCI

controller is performed through the PCnet-PCI control-

lers Register Data Port (RDP). In order to access a par-

ticular CSR location, the Register Address Port (RAP)

should first be written with the appropriate CSR ad-

dress. The RDP now points to the selected CSR. A read

of the RDP will yield the selected CSRs data. A write to

the RDP will write to the selected CSR.

When programmed for WIO mode, the RDP has a width

of 16 bits, hence, all CSR locations have 16 bits of width.

Note that when accessing RDP, the upper two bytes of

the data bus will be undefined since the byte masks will

not be active for those bytes.

If DWIO mode has been invoked, then the RDP has a

width of 32 bits, hence, all CSR locations have 32 bits of

width and the upper two bytes of the data bus will be ac-

tive, as indicated by the byte mask. In this case, note

that the upper 16 bits of all CSR locations (except

CSR88) are reserved and written as ZEROs and read as

undefined values. Therefore, during RDP write opera-

tions in DWIO mode, the upper 16 bits of all CSR loca-

tions should be written as ZEROs.

RAP Access

RAP = Register Address Port. The RAP is used with the

RDP and with the BDP to gain access to any of the CSR

and BCR register locations, respectively. The RAP con-

tains the address pointer that will be used by an access

to either the RDP or BDP. Therefore, it is necessary to

set the RAP value before accessing a specific CSR or

BCR location. Once the RAP has been written with a

value, the RAP value remains unchanged until another

RAP write occurs, or until an H_RESET or S_RESET

occurs. RAP is set to all ZEROs when an H_RESET or

S_RESET occurs. RAP is unaffected by the STOP bit.

When programmed for WIO mode, the RAP has a width

of 16 bits. Note that when accessing RAP, the lower two

bytes of the data bus will be undefined since the byte

masks will not be active for those bytes

When programmed for DWIO mode, the RAP has a

width of 32 bits. In DWIO mode, the upper 16 bits of the

RAP are reserved and written as ZEROs and read as

undefined. These bits should be written as ZEROs.

BDP Access (BCR Register Space)

BDP = Bus Configuration Register Data Port. The BDP

is used with the RAP to gain access to any of the PCnet-

PCI controller BCR locations.

Access to any of the BCR locations of the PCnet-PCI

controller is performed through the PCnet-PCI control-

lers BCR Data Port (BDP ); in order to access a particu-

lar BCR location, the Register Address Port (RAP)

should first be written with the appropriate BCR ad-

dress. The BDP now points to the selected BCR.

A read of the BDP will yield the selected BCR s data. A

write to the BDP will write to the selected BCR.

When programmed for WIO mode, the BDP has a width

of 16 bits, hence, all BCR locations have 16 bits of width

in WIO mode. Note that when operating in WIO mode,

AM79C970 数据表(PDF) 65 Page - Advanced Micro Devices

AM79C970 数据表(HTML) 65 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载