AM79C970 datasheet(37/168 Pages) AMD

37 / 168 page

AMD

P R E L I M I N A R Y

1-904

Am79C970

FIFO DMA Transfers

PCnet-PCI microcode will determine when a FIFO DMA

transfer is required. This transfer mode will be used for

transfers of data to and from the PCnet-PCI FIFOs.

Once the PCnet-PCI BIU has been granted bus maste-

rship, it will perform a series of consecutive transfer cy-

cles before relinquishing the bus. All transfers within the

master cycle will be either read or write cycles, and all

transfers will be to contiguous, ascending addresses.

Both non-burst and burst cycles are used.

Non-Burst FIFO DMA Transfers

Non-burst FIFO DMA transfers is the default mode the

PCnet-PCI controller uses to read and write data when

accessing the FIFOs. Each non-burst transfer will be

performed sequentially, with the issue of an address,

and the transfer of the corresponding data with appropri-

ate output signals to indicate selection of the active data

bytes during the transfer.

FRAME will be dropped after

every address phase. (See figures 2,3 and 5.) The num-

ber of data transfer cycles contained within a single bus

mastership period is in general dependent on the pro-

gramming of the DMAPLUS option (CSR4, bit 14). Sev-

eral other factors will also affect the length of the bus

mastership period. The possibilities are as follows:

If DMAPLUS = 0, a maximum of 16 transfers will

be performed by default. This default value may be

changed by writing to the DMA Transfer Counter

(CSR80). Note that DMAPLUS = 0 merely sets a

maximum value. The minimum number of transfers

in the bus mastership period will be determined by

all of the following variables: the settings of the

FIFO watermarks and the conditions of the FIFOs,

the value of the DMA Transfer Counter (CSR80),

the value of the DMA Bus Timer (CSR82), and any

occurrence of preemption that takes place during

the bus mastership period.

If DMAPLUS = 1, the bus cycle will continue until

the transmit FIFO is filled to its high threshold

(read transfers) or the receive FIFO is emptied to

its low threshold (write transfers), or until the DMA

Bus Timer value (CSR82) has expired. Other vari-

ables may also affect the end point of the bus ma-

stership period in this mode. Among those

variables are the particular conditions existing

within the FIFOs, receive and transmit status con-

ditions, and bus preemption events.

The FIFO thresholds are programmable (see descrip-

tion of CSR80), as are the DMA Transfer Counter and

Bus Timer values. The exact number of transfer cycles

in the case of DMAPLUS = 1 will be dependent on the

latency of the system bus to the PCnet-PCI controller’s

mastership request and the speed of bus operation, but

will be limited by the value in the Bus Timer register, the

FIFO condition, receive and transmit status, and by

preemption events. Barring a time-out by either of these

registers, or a bus preemption by another mastering de-

vice, or exceptional receive and transmit events, or an

end of packet signal from the FIFO, the FIFO watermark

settings and the extent of Bus Grant latency will be the

major factors determining the number of accesses per-

formed during any given arbitration cycle when

DMAPLUS = 1.

The

TRDY response of the memory device will also af-

fect the number of transfers when DMAPLUS = 1, since

the speed of the accesses will affect the state of the

FIFO. (During accesses, the FIFO may be filling or emp-

tying on the network end. A slower memory response

will allow additional data to accumulate inside of the

FIFO (during write transfers from the receive FIFO). If

the accesses are slow enough, a complete DWORD

may become available before the end of the arbitration

cycle and thereby increase the number of transfers in

that cycle.) The general rule is that the longer the Bus

Grant latency or the slower the bus transfer operations

(or clock speed) or the higher the transmit watermark or

the lower the receive watermark or any combination

thereof the longer will be the average bus mastership

period.

Burst FIFO DMA Transfers

Bursting is only performed by the PCnet-PCI controller if

the BREADE and/or BWRITE bits of BCR18 are set.

These bits individually enable/disable the ability of the

PCnet-PCI controller to perform burst accesses during

master read operations and master write operations, re-

spectively. Only FIFO data transfers will make use of the

burst mode.

The first transfer in the burst will consist of both an ad-

dress and a data phase. Subsequent transfers will con-

tain data only. AD[1:0] will always be ZERO during the

address phase indicating a linear burst order. Note, that

the terms ‘burst’ and ‘linear burst’ are used interchange-

ably throughout this document.

The number of data phases within the burst transfer is

determined by the LINBC value from the BCR18 regis-

ter. The burst upper limit is calculated by taking the

BCR18 LINBC[2:0] value and multiplying it by 4. The re-

sult is the number of transfers that will be performed

within a single linear burst sequence. When the LINBC

upper limit of data transfers have been performed, a

new

FRAME may be asserted (if there is more data to be

transferred), with a new address on the AD pins. Follow-

ing the assertion of a new

FRAME, the linear bursting of

data will resume. All byte lanes will always be active dur-

ing all burst transfers as reflected by the C/

BE[3:0]

signals.

The number of data transfer cycles within the total bus

mastership period is dependent on the programming of

the DMAPLUS option (CSR4, bit 14). The possibilities

are as follows:

AM79C970 数据表(PDF) 37 Page - Advanced Micro Devices

AM79C970 数据表(HTML) 37 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载