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AM79C970 数据表(PDF) 102 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 102 Page - Advanced Micro Devices |
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102 / 168 page  P R E L I M I N A R Y AMD 1-969 Am79C970 CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXDAL Contains the lower 16 bits of the previous TDRE address pointer. PCnet-PCI controller has the ca- pability to stack multiple transmit frames. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR61: Previous Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXDAU Contains the upper 16 bits of the previous TDRE address pointer. PCnet-PCI controller has the ca- pability to stack multiple transmit frames. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR62: Previous Transmit Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZERO. Accessible only when STOP bit is set. 11–0 PXBC Previous Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the previous transmit descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR63: Previous Transmit Status Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 PXST Previous Transmit Status. This field is a copy of bits 31–24 of TMD1 of the previous transmit descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. 7–0 RES Reserved locations. Read and written as ZERO. Accessible only when STOP bit is set. CSR64: Next Transmit Buffer Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXBAL Contains the lower 16 bits of the next transmit buffer address from which the PCnet-PCI controller will transmit an outgoing frame. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR65: Next Transmit Buffer Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXBAU Contains the upper 16 bits of the next transmit buffer address from which the PCnet-PCI controller will transmit an outgoing frame. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR66: Next Transmit Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZERO. Accessible only when STOP bit is set. 11–0 NXBC Next Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the next transmit de- scriptor. |
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