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AM79C970 数据表(PDF) 103 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 103 Page - Advanced Micro Devices |
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103 / 168 page  AMD P R E L I M I N A R Y 1-970 Am79C970 Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR67: Next Transmit Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 NXST Next Transmit Status. This field is a copy of bits 31–24 of TMD1 of the next transmit descriptor. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. 7–0 RES Reserved locations. Read and written as ZERO. Accessible only when STOP bit is set. CSR72: Receive Ring Counter Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 RCVRC Receive Ring Counter location. Contains a Two’s complement binary number used to number the current receive descriptor. This counter interprets the value in CSR76 as pointing to the first descriptor. A counter value of ZERO corresponds to the last descriptor in the ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR74: Transmit Ring Counter Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 XMTRC Transmit Ring Counter location. Contains a Two’s complement binary number used to number the current transmit descriptor. This counter interprets the value in CSR78 as pointing to the first descriptor. A counter value of ZERO corresponds to the last descriptor in the ring. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR76: Receive Ring Length Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 RCVRL Receive Ring Length. Contains the two’s complement of the re- ceive descriptor ring length. This register is initialized during the PCnet-PCI initialization routine based on the value in the RLEN field of the initialization block. However, this register can be manually altered. The actual re- ceive ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR78: Transmit Ring Length Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 XMTRL Transmit Ring Length. Contains the two’s complement of the transmit descriptor ring length. This register is initialized during the PCnet-PCI initialization rou- tine based on the value in the TLEN field of the initialization block. However, this register can be manually altered. The actual transmit ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET or STOP. CSR80: DMA Transfer Counter and FIFO Thresh- old Control Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–14 RES Reserved locations. Read as ones and written as ZERO. |
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