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AM79C970 数据表(PDF) 104 Page - Advanced Micro Devices |
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AM79C970 数据表(HTML) 104 Page - Advanced Micro Devices |
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104 / 168 page ![]() P R E L I M I N A R Y AMD 1-971 Am79C970 13–12 RCVFW[1:0] Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation to the number of re- ceived bytes in the receive FIFO. RCVFW specifies the number of bytes which must be present (once the frame has been veri- fied as a non-runt) before receive DMA is requested. Note however that in order for receive DMA to be performed for a new frame, at least 64 bytes must have been received. This effectively avoids having to react to receive frames which are runts or suffer a colli- sion during the slot time (512 bit times). If the Runt Packet Accept feature is enabled, receive DMA will be requested as soon as either the RCVFW threshold is reached, or a complete valid re- ceive frame is detected (regard- less of length). RCVFW is set to a value of 10b (64 bytes) after H_RESET or S_RESET and is unaffected by STOP. RCVFW[1:0] Bytes Received 00 16 01 32 10 64 11 Reserved Read/write accessible only when STOP bit is set. Certain combinations of water- mark programming and LINBC (BCR18, bits 2–0) programming may create situations where no linear bursting is possible, or where the FIFO may be exces- sively read or excessively writ- ten. Such combinations are declared as illegal. Combinations of watermark set- tings and LINBC (BCR 18, bits 2–0) settings must obey the fol- lowing relationship: watermark (in bytes) ≥ LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. 11–10 XMTSP[1:0] Transmit Start Point. XMTSP controls the point at which pre- amble transmission attempts commence in relation to the num- ber of bytes written to the transmit FIFO for the current transmit frame. When the entire frame is in the FIFO, transmis- sion will start regardless of the value in XMTSP. XMTSP is given a value of 10b (64 bytes) after H_RESET or S_RESET and is unaffected by STOP. Regardless of XMTSP, the FIFO will not internally over write its data until at least 64 bytes (or the entire frame if < 64 bytes) have been transmitted onto the network. This ensures that for collisions within the slot time window, transmit data need not be re-written to the transmit FIFO, and re-tries will be handled autonomously by the MAC. This bit is read/write accessible only when the STOP bit is set. XMTSP[1:0] Bytes Written 00 4 01 16 10 64 11 112 9–8 XMTFW[1:0] Transmit FIFO Watermark. XMTFW specifies the point at which transmit DMA stops, based upon the number of write cycles that could be performed to the transmit FIFO without FIFO overflow. Transmit DMA is al- lowed at any time when the num- ber of write cycles specified by XMTFW could be executed with- out causing transmit FIFO over- flow. XMTFW is set to a value of 00b (8 cycles) after H_RESET or S_RESET and is unaffected by STOP. Read/write accessible only when STOP bit is set. XMTFW[1:0] Bytes Written 00 16 01 32 10 64 11 Reserved Certain combinations of water- mark programming and LINBC (BCR18, bits 2–0) programming may create situations where no linear bursting is possible, or where the FIFO may be exces- sively read or excessively writ- ten. Such combinations are declared as illegal. |
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