ST7DALIF2 datasheet(52/171 Pages) STMICROELECTRONICS

52 / 171 page

Power saving modes

ST7DALIF2

52/171

Figure 22.

Wait mode flowchart

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

11.4

Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by

executing the ‘HALT’ instruction when Active-Halt is disabled (see Section 11.5 on page 54

for more details) and when the AWUEN bit in the AWUCSR register is cleared.

The MCU can exit Halt mode on reception of either a specific interrupt (see Table 15:

Interrupt mapping on page 47) or a RESET. When exiting Halt mode by means of a RESET

or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay

is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by

servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24).

When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,

including the operation of the on-chip peripherals. All peripherals are not clocked except the

ones which get their clock supply from another clock generator (such as an external or

auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the Watchdog

system is enabled, can generate a Watchdog RESET (see Section 22.1 on page 161 for

more details).

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

CPU

OSCILLATOR

PERIPHERALS

IBIT

X 1)

CYCLE DELAY

256 OR 4096 CPU CLOCK

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