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ST7DALIF2 数据表(PDF) 33 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 33 Page - STMicroelectronics

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ST7DALIF2
Supply, reset and clock management
33/171
Note:
1
Section 20: Electrical characteristics on page 127 for more information on the frequency
and accuracy of the RC oscillator.
2
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
3
These two bytes are systematically programmed by ST, including on FASTROM devices.
Consequently, customers intending to use FASTROM service must not use these two bytes.
4
RCCR0 and RCCR1 calibration values will be erased if the readout protection bit is reset
after it has been set. See Readout protection on page 21
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
9.3
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain fOSC2 of 4 or 8 MHz. The PLL is enabled and the multiplication
factor of 4 or 8 is selected by 2 option bits.
The x4 PLL is intended for operation with VDD in the 2.4 V to 3.3 V range
The x8 PLL is intended for operation with VDD in the 3.3 V to 5.5 V range
Refer to Section 22.1 on page 161 for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then fOSC2 = 1 MHz.
If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.
Table 9.
RC control registers
RCCR
Conditions
ST7DALI address
RCCR0
VDD=5V
TA=25°C
fRC=1MHz
1000h
and FFDEh
RCCR1
VDD=3V
TA=25°C
fRC=700KHz
1001h
and FFDFh



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