ST7DALIF2 datasheet(94/171 Pages) STMICROELECTRONICS

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DALI communication module

ST7DALIF2

94/171

16.8

Low power modes

16.9

Interrupts

16.10

Bi-phase bit detection

The clock used for sampling the DALI signal is programmed by the DCMCLK register. Each

bit phase is sampled 16 times. The bit phase level is determined by two of three sample

clock pulses (pulses 6,7,8). The two phase levels of the bi-phase bit are shifted into the 4-bit

pre-shift register at the 9th sample clock pulse.

Only the second phase level of the bi-phase bit is shifted into the 16-bit shifter.

The 4-bit pre-shifter is used to detect any errors in the received frame.

When a change of phase is detected (edge trigger), the 4-bit sample clock counter (integer

range 0 to15) is cleared.

Table 43.

Effect of low power modes on DCM

Mode

Description

Wait

No effect on DCM

Halt

DCM registers are frozen

Active-halt

No effect on DCM

Table 44.

Interrupt control bits

Interrupt event

Event

flag

Enable

control

bit

Exit

from

Wait

Exit

from

Halt

EOT

ITF

ITE

Yes

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