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ST7DALIF2 数据表(PDF) 97 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 171 page  ST7DALIF2 DALI communication module 97/171 Bits 7:0 = DCMFA[7:0] Forward Address. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" address byte. 16.11.3 DCM forward data register (DCMFD) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = DCMFD[7:0] Forward Data. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" data byte. 16.11.4 DCM backward data register (DCMBD) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = DCMBD[7:0] Backward Data. These bits are set/cleared by software and cleared by hardware after a reset. These 8 bits are used to store the "backward frame" data byte. The software writes to this register before enabling the transmit operation. 16.11.5 DCM control register (DCMCR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = DCME DALI Communication Enable. This bit is set/cleared by software and cleared by hardware after a reset. When set, it enables DALI communication. It also resets the entire internal finite state machine. 0: The DCM is not enable to receive/transmit 1: The DCM is enable to receive/transmit Bit 2 = RTA Receive/Transmit Acknowledge. This bit is reset by hardware after it has been set by software. It is cleared after a reset. This bit must be set, after a first DALI frame reception or transmission, to allow the DCM to perform the next DALI communication. 0: No acknowledge 7 0 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 7 0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 7 0 0000 DCME RTA RTS FTS |
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