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ST7DALIF2 数据表(PDF) 96 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 171 page  DALI communication module ST7DALIF2 96/171 Figure 44. Example of DALI signal sampling 16.11 Register description 16.11.1 DCM data rate control register (DCMCLK) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = DCMCLK[7:0] Clock Prescaler. These bits are set/cleared by software and cleared by hardware after a reset. These 8 bits are used for tuning the DALI data rate. fDATA = fCPU/[(N+1)*16] where N is the integer value of the DCMCLK register. 16.11.2 DCM forward address register (DCMFA) Read only Reset Value: 0000 0000 (00h) DALI Signal Edge Trigger tCPU tCPU tCPU 4-bit sample clock counter (/16 divider) 0000 0001 1111 0000 xxxx 0000 0000 1111 xxxx DCMCSR[3:0] bits tCPU= f CPU m 1 m = (DCMCLK integer value+1) x tCPU fDALI= 1.2 kHz N = 207 (DCMCLK) fCPU= 8 MHz tCPU = 125ns m = 26 µs (208 x 125ns) Example: Legend: 833.33µs 7 0 CK7 CK6 CK5 CK4 CK3 CK2 CK1 CK0 7 0 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 |
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