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ST7DALIF2 数据表(PDF) 53 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 171 page  ST7DALIF2 Power saving modes 53/171 Figure 23. Halt mode timing overview Figure 24. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 15: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 11). HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [Active Halt disabled] RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) IBIT OFF OFF 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF X 4) ON CPU OSCILLATOR PERIPHERALS IBIT ON ON X 4) ON 256 OR 4096 CPU CLOCK DELAY5) WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 CYCLE HALT INSTRUCTION (Active-halt disabled) (AWUCSR.AWUEN=0) |
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