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ST7DALIF2 数据表(PDF) 79 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 171 page  ST7DALIF2 12-bit autoreload timer 2 (AT2) 79/171 software should read the counter value in two consecutive read operations. The CNTRH register can be incremented between the two reads, and in order to be accurate when fTIMER=fCPU, the software should take this into account when CNTRL and CNTRH are read. If CNTRL is close to its highest value, CNTRH could be incremented before it is read When a counter overflow occurs, the counter restarts from the value specified in the ATR register. 14.6.4 Autoreload register (ATRH) Read / Write Reset Value: 0000 0000 (00h) 14.6.5 Autoreload register (ATRL) Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency. 14.6.6 PWM output control register (PWMCR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = OE[3:0] PWMx output enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx output alternate function disabled: I/O pin free for general purpose I/O after an overflow event. 1: PWM mode enabled 14.6.7 PWMx control status register (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2= Reserved, must be kept cleared. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 7 0 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 7 0 0OE3 0 OE20OE1 0OE0 76 0 000 000 OPx CMPFx |
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