ST7DALIF2 datasheet(80/171 Pages) STMICROELECTRONICS

80 / 171 page

12-bit autoreload timer 2 (AT2)

ST7DALIF2

80/171

Bit 1 = OPx PWMx Output Polarity.

This bit is read/write by software and cleared by hardware after a reset. This bit selects the

polarity of the PWM signal.

0: The PWM signal is not inverted.

1: The PWM signal is inverted.

Bit 0 = CMPFx PWMx Compare Flag.

This bit is set by hardware and cleared by software by reading the PWMxCSR register. It

indicates that the upcounter value matches the DCRx register value.

0: Upcounter value does not match DCR value.

1: Upcounter value matches DCR value.

14.6.8

Break control register (BREAKCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:6 = Reserved. Forced by hardware to 0.

Bit 5 = BA Break Active.

This bit is read/write by software, cleared by hardware after reset and set by hardware when

the BREAK pin is low. It activates/deactivates the Break function.

0: Break not active

1: Break active

Bit 4 = BPEN Break Pin Enable.

This bit is read/write by software and cleared by hardware after Reset.

0: Break pin disabled

1: Break pin enabled

Bits 3:0 = PWM[3:0] Break Pattern.

These bits are read/write by software and cleared by hardware after a reset. They are used

to force the four PWMx output signals into a stable state when the Break function is active.

14.6.9

PWMx duty cycle register high (DCRxH)

Read / Write

Reset Value: 0000 0000 (00h)

BPEN

PWM3

PWM2

PWM1

PWM0

DCR11

DCR10

DCR9

DCR8

ST7DALIF2 数据表(PDF) 80 Page - STMicroelectronics

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