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ST7DALIF2 数据表(PDF) 67 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 67 Page - STMicroelectronics |
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67 / 171 page ![]() ST7DALIF2 I/O ports 67/171 12.7 Device-specific I/O port configuration The I/O port register configurations are summarized as follows. Table 29. Ports PA7:0, PB6:0 with interrupt capability not selected in EISR register Mode DDR OR floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 Table 30. Ports PA7:0, PB6:0 with interrupt capability selected in EISR register Mode DDR OR Floating input 0 0 Pull-up interrupt input 0 1 Open drain output 1 0 Push-pull output 1 1 Table 31. Port configuration (interrupt capability not selected in the EISR register) Port Pin name Input Output OR = 0 OR = 1 OR = 0 OR = 1 Port A PA7:0 floating pull-up open drain push-pull Port B PB6:0 floating pull-up open drain push-pull Table 32. Port configuration (interrupt capability selected in the EISR register) Port Pin name Input Output OR = 0 OR = 1 OR = 0 OR = 1 Port A PA7:0 floating pull-up interrupt open drain push-pull Port B PB6:0 floating pull-up interrupt open drain push-pull Table 33. I/O port register map and reset values Address (Hex.) Register label 76543210 0000h PADR Reset Value MSB 1111111 LSB 1 0001h PADDR Reset Value MSB 0000000 LSB 0 0002h PAOR Reset Value MSB 0100000 LSB 0 |
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