ST7DALIF2 datasheet(93/171 Pages) STMICROELECTRONICS

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ST7DALIF2

DALI communication module

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If the software asks the DCM to receive a "forward frame", the software must switch the

DCM to Receive state by clearing the RTS bit and setting the RTA bit in the DCMCR register

during the interrupt routine.

If the ITF interrupt flag is set in the DCMCSR register, the software must set the RTA bit in

the DCMCR register to allow the DCM to perform the next DALI signal reception or

transmission.

The DALIIN signal is always taken into account by the 4-bit pre-shifter.

16.6

Special functions

16.6.1

Forced transmission (test mode)

The DCM must receive a "forward frame" before sending back a "backward frame". But it is

possible to force the DCM into Transmit state by setting the FTS bit in the DCMCR register.

The DCMBD register will be shifted out in DALI format, the Most Significant Bit-first.

Preferably before forcing the DCM into Transmit state, the user should reset/set the DCME

bit in the DCMCR register. An interrupt flag will be generated after a forced transmission (the

ITF bit in the DCMCSR register).

Procedure:

– Reset the DCME bit in the DCMCR register.

– Write the backward value in the DCMBD register.

– Set both the DCME and the FTS bits in the DCMCR register.

– When an interrupt is generated (end of transmission, the ITF bit is set in the

DCMCSR register), set the RTA bit in the DCMCR register to re-start a transmission.

– To return to normal DALI communications, reset/set the DCME bit and reset the FTS

bit in the DCMCR register.

16.6.2

Normal transmission

After the "forward frame" reception, the software must write the backward data byte to the

DCMBD register and set both the RTS and RTA bits in the DCMCR register to start the

transmission.

It is not possible to send a backward frame just after having sent a backward frame (see

DALI standard protocol).

16.6.3

DCM enable

The user can enable or disable the DCM by writing the DCME bit in the DCMCR register.

This bit is also used to reset the entire internal finite state machine.

16.7

DALI interface failure

If the DALI input signal is set to low level for a 2-bit period (1.66 ms), then the DCM

generates an error flag by setting the EF bit in the DCMCSR register. This bit can be cleared

by reading the DCMCSR register. The interface failure is detected if the DCM is in Receive

state only.

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