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ST7DALIF2 数据表(PDF) 82 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 171 page  12-bit autoreload timer 2 (AT2) ST7DALIF2 82/171 14.6.13 Transfer control register (TRANCR) Read/Write Reset Value: 0000 0001 (01h) Bits 7:1 Reserved. Forced by hardware to 0. Bit 0 = TRAN Transfer enable This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It allows the value of the DCRx registers to be transferred to the DCRx shadow registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. 7 0 00 00000 TRAN Table 39. Register map and reset values Address (Hex.) Register label 7654 3210 0D ATCSR Reset Value 0 ICF 0 ICIE 0 CK1 0 CK0 0 OVF 0 OVFIE 0 CMPIE 0 0E CNTRH Reset Value 0000 CNTR1 1 0 CNTR1 0 0 CNTR9 0 CNTR8 0 0F CNTRL Reset Value CNTR7 0 CNTR8 0 CNTR7 0 CNTR6 0 CNTR3 0 CNTR2 0 CNTR1 0 CNTR0 0 10 ATRH Reset Value 0000 ATR11 0 ATR10 0 ATR9 0 ATR8 0 11 ATRL Reset Value ATR7 0 ATR6 0 ATR5 0 ATR4 0 ATR3 0 ATR2 0 ATR1 0 ATR0 0 12 PWMCR Reset Value 0 OE3 0 0 OE2 0 0 OE1 0 0 OE0 0 13 PWM0CSR Reset Value 0000 00 OP0 0 CMPF0 0 14 PWM1CSR Reset Value 0000 00 OP1 0 CMPF1 0 15 PWM2CSR Reset Value 0000 00 OP2 0 CMPF2 0 |
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