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ST7DALIF2 数据表(PDF) 44 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 44 Page - STMicroelectronics

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Supply, reset and clock management
ST7DALIF2
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9.7.4
Register description
System integrity (SI) control/status register (SICSR)
Read/Write
Reset Value: 0000 0xx0 (0xh)
Bit 7:5 = Reserved, must be kept cleared.
Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following
table.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set automatically when the PLL reaches its
operating frequency.
0: PLL not locked
1: PLL locked
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware
(LVD reset) and cleared by software (by reading). When the LVD is disabled by OPTION
BYTE, the LVDRF bit value is undefined.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request
is generated when the AVDF bit is set. Refer to Figure 18 and to Monitoring the VDD main
supply on page 42 for additional details.
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when software
enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Note:
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
7
0
0
0
0
WDGRF
LOCKED
LVDRF
AVDF
AVDIE
Table 14.
Reset flags
RESET sources
LVDRF
WDGRF
External RESET pin
0
0
Watchdog
0
1
LVD
1
X



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